Patent
Method for fabrication of improved bipolar injection logic circuit
TLDR
In this article, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate by implanting P-type impurity in a location spaced apart from the surfaces of the epitaxia layer.Abstract:
An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.read more
Citations
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Patent
Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
TL;DR: A process of fabricating semiconductor devices involving plural epitaxial layer growth steps is described in this paper, where the authors describe the process of constructing a semiconductor device with a number of growth steps.
Patent
High speed lateral bipolar transistor
Martin P Lepselter,Simon M. Sze +1 more
TL;DR: In this paper, a bipolar transistor NPN structure is constructed at a major surface of a silicon body with a P-type polycrystalline silicon electrode (13) contacting a P type base zone (13.6).
Patent
Process for fabricating complementary contactless vertical bipolar transistors
TL;DR: In this article, a complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P-- tub for NPN; (2) a channel stopper for NP, and a ground for PNP; (3) a sink for NP and ground for NP; (4) a base for NP.
Patent
Method for fabrication vertical NPN and PNP structures utilizing ion-implantation
TL;DR: In this paper, a method for fabricating vertical NPN and PNP structures on the same semiconductor body is presented, which involves providing a monocrystalline semiconductor substrate having regions of monocrystine silicon isolated from one another by isolation regions.
Patent
GaAs/GaAlAs Heterojunction bipolar integrated circuit devices
TL;DR: The use of an ion implant technique avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with ion implantation, makes possible the fabrication of IC quality transistors consistently over a substrate as mentioned in this paper.
References
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Patent
Monolithic semiconductor circuit for a logic circuit concept of high packing density
Berger Horst Dipl-Ing,S Wiedmann +1 more
TL;DR: In this article, a monolithic semiconductor circuit consisting of a lateral PNP transistor and an inversely operated vertical NPN transistor is described, where the collector region is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body.
Journal ArticleDOI
Integrated injection logic-present and future
TL;DR: Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistor as invertors, are discussed.
Patent
Multilayered vertical transistor having reach-through isolating contacts
Berger H,S Wiedmann +1 more
TL;DR: In this article, a logic circuit consisting of a PNP transistor and an NPN transistor is proposed to perform the INVERTER and NOR functions, and two such basic circuits are interconnected to provide the NOR function.
Patent
Monolithically integrable digital basic circuit
TL;DR: In this paper, a switching transistor is employed, whose emitter terminal is connected to a voltage source and whose collector and base are linked with the base and the emitter of the switching transistor respectively.
Patent
Method of manufacturing semi-conductor devices
TL;DR: In this paper, a method for making a semiconductor device in which in a hole in an insulating layer on the surface of the semiconductor is provided a metal layer in a self-registered manner so as to fill the hole and overlap at least on the edge of the insulating layers is described.