Proceedings ArticleDOI
Multiple single input change test vector for BIST schemes
V. Selva Kumar,Janani S. Mohan +1 more
- pp 1-4
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TLDR
A novel test pattern generator (TPG) called multiple single input change (MSIC) TPG for test the modules of the chip for uniform distribution and low transition density is introduced.Abstract:
In VLSI Industry testing is an essential process for making the assurance functionality of the chip. This paper is focusing one of the test methodology called built-in-self-test (BIST). To introduce a novel test pattern generator (TPG) called multiple single input change (MSIC) TPG for test the modules of the chip. This TPG generates single input change (SIC) test vectors in multiple scan chains. Scan chains count is equal to the number of modules inside the chip. MSIC test vectors are generated here with a re-configurable Johnson counter and a fixed seed values. Seed is a pre-defined bit for MSIC pattern generator based on the modules available in the chip. Bit EX-OR operation is performed between the Re-configurable Johnson counter and the seed. Analysis result shows that the produced MSIC sequences have the features of uniform distribution and low transition density. Simulation results with S344 benchmark demonstrate that MSIC can save the test power by 7.5%.read more
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Book ChapterDOI
Design of TPG BIST Using Various LFSR for Low Power and Low Area
TL;DR: In this paper , different LFSR structures such as Modular L FSR, cellular Automation pattern generator, LT-LFSR and LT-RTPG were designed and compared with standard L FSRs for parameters such as area, power, bit transitions and delay.
Proceedings ArticleDOI
Configurable Built-In Self-Test Architecture for Automated Testing of a Dual-Axis Solar Tracker
Raul Rotar,Sorin Liviu Jurj +1 more
TL;DR: In this article, the authors present two manually configurable test architectures, which, due to their compact design and restructuring capabilities, allow for facile deployment in today's automation systems.
References
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Survey of low-power testing of VLSI circuits
TL;DR: The author reviews low-power testing techniques for VLSI circuits with a discussion of power consumption that gives reasons for and consequences of increased power during test.
Proceedings ArticleDOI
Survey of low power testing of VLSI circuits
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Proceedings ArticleDOI
A gated clock scheme for low power scan testing of logic ICs or embedded cores
TL;DR: A novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores is presented, based on a gated clock scheme for the scan path and the clock tree feeding thescan path.
Journal ArticleDOI
Low-power scan design using first-level supply gating
TL;DR: A novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops.
Journal ArticleDOI
DS-LFSR: a BIST TPG for low switching activity
TL;DR: A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed, which consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed L FSR.