Proceedings ArticleDOI
A gated clock scheme for low power scan testing of logic ICs or embedded cores
Y. Bonhomme,Patrick Girard,L. Guiller,Christian Landrault,Serge Pravossoudovitch +4 more
- pp 253-258
TLDR
A novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores is presented, based on a gated clock scheme for the scan path and the clock tree feeding thescan path.Abstract:
Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.read more
Citations
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Journal ArticleDOI
Survey of low-power testing of VLSI circuits
TL;DR: The author reviews low-power testing techniques for VLSI circuits with a discussion of power consumption that gives reasons for and consequences of increased power during test.
Journal ArticleDOI
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction
TL;DR: A scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches and achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time.
Proceedings ArticleDOI
CASP: concurrent autonomous chip self-test using stored test patterns
TL;DR: CASP enables design of robust systems with built-in features for circuit failure prediction, error detection, self-diagnosis and self-repair to overcome major reliability challenges in scaled-CMOS technologies.
Book
System-on-Chip Test Architectures: Nanometer Design for Testability
TL;DR: This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V LSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Journal ArticleDOI
RL-huffman encoding for test compression and power reduction in scan applications
Mehrdad Nourani,M.H. Tehranipour +1 more
TL;DR: This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan test applications by using run-length encoding followed by Huffman encoding.
References
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Proceedings ArticleDOI
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Proceedings ArticleDOI
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Proceedings ArticleDOI
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