Multiplexer based adder for media signal processing

TLDR: The design of a highly re-configurable adder, which has been optimized for speed and area, is presented, which is the hybrid of binary carry lookahead adder of Brent, and carry select adder.

Abstract: This paper presents the design of a highly re-configurable adder, which has been optimized for speed and area. Since pass transistor based multiplexer is the fastest element in standard CMOS logic, we designed the adder using only multiplexers and 2-input inverted logic gates. This adder is the hybrid of binary carry lookahead adder of Brent, and carry select adder. By using the hybrid approach, the area and wiring of the adder is reduced by 1/2, keeping the adder delay proportional to O(log n). The critical path of the 68-bit partitioned adder consists of 7 two-to-one multiplexers and 1 XOR gate. The adder can be partitioned to support a variety of data formats, it can add two 64-bit-operands, four 32-bit operands, eight 16-bit operands, or sixteen and bit operands. The adder can be used for multi-media applications, and is well suited for VLIW processors. The adder is described in Verilog, and synthesized using Synopsys tool. The critical path delay of the 64-bit adder is 0.9 ns at typical conditions in standard cell 0.25 um technology.