Università
della
Svizzera
italiana
USI Technical Report Series in Informatics
Net-aware Critical Area Extraction for Opens in VLSI Circuits via Higher
Order Voronoi Diagrams
Evanthia Papadopoulou
1
1
Faculty of Informatics, Università della Svizzera italiana, Switzerland
Abstract
We address the problem of computing critical area for open faults (opens) in a circuit
layout in the presence of multilayer loops and redundant interconnects. The extrac-
tion of critical area is the main computational bottleneck in predicting the yield loss
of a VLSI design due to random manufacturing defects. We first model the problem as
a geometric graph problem and we solve it efficiently by exploiting its geometric na-
ture. To model open faults we formulate a new geometric version of the classic min-cut
problem in graphs, termed the geometric min-cut problem. Then the critical area ex-
traction problem gets reduced to the construction of a generalized Voronoi diagram for
open faults, based on concepts of higher order Voronoi diagrams. The approach ex-
pands the Voronoi critical area computation paradigm [5, 16–19, 22, 28] with the ability
to accurately compute critical area for missing material defects even in the presence
of loops and redundant interconnects spanning over multiple layers. The generalized
Voronoi diagrams used in the solution are combinatorial structures of independent in-
terest.
Report Info
Published
June 2010
Number
USI-INF-TR-2010-6
Institution
Faculty of Informatics
Università della Svizzera italiana
Lugano, Switzerland
Online Access
www.inf.usi.ch/techreports
1 Introduction
Catastrophic yield loss of integrated circuits is caused to a large extent by random particle defects interfe-
ring with the manufacturing process resulting in functional failures such as open or short circuits. Yield loss
due to random manufacturing defects has been studied extensively in both industry and academia and se-
veral yield models for random defects have been proposed (see e.g., [8,25,26]). The focus of all models is the
concept of critical area, a measure reflecting the sensitivity of a design to random defects during manufactu-
ring. Reliable critical area extraction is essential for today’s IC manufacturing especially when DFM (Design
for Manufacturability) initiatives are under consideration.
The critical area of a circuit layout on a layer A is defined as
A
c
=
Z
∞
0
A(r )D(r )d r
where A(r ) denotes the area in which the center of a defect of radius r must fall in order to cause a circuit
failure and D(r ) is the density function of the defect size. The defect density function has been estimated as
follows [8, 12, 25, 29]:
D(r ) =
¨
c r
q
/r
q+1
0
, 0 ≤ r ≤ r
0
c r
p−1
0
/r
p
, r
0
≤ r ≤ ∞
(1)
where p,q are real numbers (typically p = 3,q = 1), c = (q + 1)(p − 1)/(q + p ), and r
0
is some minimum
optically resolvable size. Using typical values for p,q, and c , the widely used defect size distribution is derived,
1
D(r ) = r
2
0
/r
3
. (r
0
is typically smaller than the minimum feature size thus, D(r ) is ignored for r < r
0
). Critical
area analysis is typically performed on a per layer basis and results are combined to estimate total yield.
In this paper we focus on critical area extraction for open faults (opens) resulting from broken intercon-
nects. Open faults are net-aware, that is, a defect causes a fault if and only if it actually breaks a net leaving
terminals disconnected. A net is said to be broken if at least one of its terminals gets disconnected. In or-
der to increase design reliability and reduce the potential for open circuits designers have been introducing
redundant interconnects creating interconnect loops that may span over a number of layers (see e.g. [11]).
Redundant interconnects reduce the potential for open faults at the expense of increasing the potential for
shorts. Therefore, the ability to perform trade-offs is important requiring accurate critical area computation
for both opens and shorts. A critical area extraction tool that fails to take loops into consideration would fal-
sely penalize designs with redundant interconnects by (erroneously) overestimating the actual critical area
for opens while (correctly) registering the increase in critical area for shorts.
In previous work on critical area extraction for open faults interconnects have been typically assumed
acyclic, that is, a defect breaking any conducting path is considered a fault (see e.g. [23], [7,16]). This assump-
tion was adequate at the time, however, it is no longer realistic. An exception is [24] where loops were being
detected and treated as immune to open faults. Critical area in [24], however, was considered strictly over
each layout shape ignoring all critical regions expanding in the free space or over other shapes resulting in
underestimation of critical area that can be arbitrarily large.
Existing methods for critical area extraction focus mostly on shorts while opens have been typically trea-
ted as a dual problem. The methods can be roughly grouped into the following categories:
1. Monte Carlo simulation, the oldest most widely used technique for critical area extraction [30].
2. Iterative shape-shifting techniques that compute A(r ) for several different values of r independently
and then use these values to extract the total critical area integral, see e.g., [2, 7, 23, 24, 32]. Shape shif-
ting techniques are typically based on shape manipulation tools providing operations such as expand-
shape-by-r and find-area for a given defect radius r (with the exception of [7,24] that are based on plane
sweep and work strictly for Manhattan geometries). For opens, the reverse process shrink-shape-by-r
is typically used, which however fails to capture several aspects of open faults. Layout sampling in
combination with shape shifting techniques were introduced in [1].
3. The Voronoi method [5,16, 18, 20, 22, 28] which is using analytical formulas to extract the entire critical
area after deriving a subdivision of the layout into regions that reveal the critical radius (size of smallest
defect) of every point. The critical area integral is typically computed with no error in a single pass of the
layout using O(n logn) type of scan line algorithms. In addition the Voronoi method can be combined
effectively with layout sampling techniques such as in [1, 4], for a fast critical area estimate at the chip
level.
4. A grid based method introduced in [29] (time complexity improved in [22]).
In this paper we focus on the Voronoi method and we expand it with the ability to detect loops and report
true open faults that are net-aware. Loops are not assumed to be immune to open faults as they can still
be broken by defects and thus they can contribute to critical area. To model open faults we first model a
VLSI net as a graph of geometric nature and we introduce a geometric version of the classic min-cut problem
in graphs, termed the geometric min-cut problem. We then solve the problem efficiently by exploiting its
geometric nature. We formulate a generalized Voronoi diagram for open faults, termed the opens Voronoi
diagram, which is based on concepts of higher order and Hausdorff Voronoi diagrams (see [18]). The Voronoi
diagram for open faults is a combinatorial structure interesting on its own right. Once the opens Voronoi
diagram on a given layer is available the entire critical area integral can be computed analytically, in linear
time, using the formulas given in [16,20,22].
The algorithms presented in this paper have been integrated in the IBM Voronoi Critical Area Analysis
tool (Voronoi CAA) [5, 28] currently used in production mode throughout IBM manufacturing. For results on
the early industrial use of Voronoi CAA and comparisons with previously available tools see [14]. An impor-
tant difference between the Voronoi method and previous geometric approaches to critical area extraction is
that it can directly compute the entire critical area integral for all possible defect radii without any repetition.
Other methods typically compute A(r ) for a specific defect radius r and then repeat for a number of radii
until they extract the entire critical area integral (see e.g. [2, 7, 23, 24, 32]). In contrast the Voronoi method
computes the critical area integral directly, using analytical formulas, resulting in no integration error and in
2
a fast deterministic method. If in addition the value of A(r ), for some specific defect radius r , is desirable, it
can be easily extracted from the corresponding Voronoi diagram requiring no additional effort. For a fast cri-
tical area estimation at the chip level the Voronoi method can be combined easily with sampling techniques,
either random [1] or deterministic [4], that sample a number of windows over the layout applying the Voronoi
critical area extraction method to a fraction only of the entire design, deriving a reliable estimate of critical
area.
The methods presented in this paper are applicable to layouts of arbitrary geometry, and do not assume
a Manhattan layout. A Manhattan layout however would result in a simpler implementation. For simplicity,
figures are depicted in Manhattan geometry. Our implementation of Voronoi CAA assumes ortho-45
1
geome-
tries in the layout. Throughout this paper defects are modeled as squares, that is, a defect of size r is modeled
as a square of radius r i.e., a square of side 2r . This corresponds to computing critical area in the L
∞
metric
2
(also known as max-norm) instead of the standard Euclidean plane. Square defects are among the most com-
mon simplifications found in critical area literature. A formal worst case bound for critical area estimation
between the L
∞
and the Euclidean metric i.e., critical area estimation between square and circular defects, is
given in [16].
The paper is organized as follows. In Section 2 we review basic concepts of Voronoi diagrams as related
to the Voronoi method for critical area extraction that are needed in subsequent sections. In Section 3 we
show how to model a net as a graph of geometric nature to facilitate the modeling of net-aware opens and the
extraction of critical area. In Section 4 we give formal definitions for a net-aware open and the opens Voronoi
diagram and define the geometric min-cut problem. In Section 5 we model the opens Voronoi diagram as
a special higher order Voronoi diagram of segments. In Section 6 we discuss the algorithm to compute the
opens Voronoi and give practical simplifications. Finally in Section7 we provide experimental results.
Once Voronoi regions of the opens Voronoi diagram are available, the critical area integral is extracted
using the formulas given in [16, 20, 22]. Since this is a known technique presented in previous literature we
refer the reader to [16, 20, 22] and we skip discussion in this paper.
2 Review of concepts of Voronoi Diagrams related to modeling opens
The Voronoi diagram of a set of polygonal sites in the plane is a partitioning of the plane into regions, one for
each site, called Voronoi regions, such that the Voronoi region of a site s is the locus of points closer to s than
to any other site. The Voronoi region of s is denoted as r e g (s ) and s is called the owner of r e g (s). The boun-
dary that borders two Voronoi regions is called a Voronoi edge, and consists of portions of bisectors between
the owners of the neighboring regions. The bisector of two polygonal objects (such as points, segments, po-
lygons) is the locus of points equidistant from the two objects. The point where three or more Voronoi edges
meet is called a Voronoi vertex. The combinatorial complexity of the ordinary Voronoi diagram of polygonal
sites is linear in the number, more precisely linear in the total combinatorial complexity, of the sites. In the
interior of a simple polygon the Voronoi diagram is known as medial axis
3
of the polygon.
Throughout this paper we use the L
∞
metric. The L
∞
distance between two points p = (x
p
,y
p
) and
q = (x
q
,y
q
) is d (p,q) = max {|x
p
− x
q
|,|y
p
− y
q
|}. In the presence of additive weights, the (weighted) dis-
tance between p and q is d
w
(p,q) = d (p,q) + w (p) + w (q), where w (p) and w (q ) denote the weights of
points p,q respectively. In case of a weighted line l , the (weighted) distance between a point t and l is
d
w
(t , l ) = min{d (t ,q) + w (q), ∀q ∈ l }. The (weighted) bisector between two polygonal elements s
i
and s
j
is
b(s
i
,s
j
) = {y | d
w
(s
i
,y ) = d
w
(s
j
,y )}. Using the L
∞
metric for critical area analysis corresponds to modeling
defects as squares.
In L
∞
, Voronoi edges and vertices can be treated as additively weighted line segments. For brevity and
in order to differentiate with ordinary line segments we use the term core segment or core element to denote
any portion of interest along an L
∞
Voronoi edge or vertex. We also use the term standard-45
◦
edges to refer
to Voronoi edges of slope ±1 that correspond to bisectors of axis parallel lines. Fig. 1 illustrates examples of
core segments. The endpoints and the open line segment portion of a core segment are differentiated and
they are treated as distinct entities.
Let s be a core segment induced by the polygonal elements e
l
, e
r
, that is, s is portion of bisector b(e
l
,e
r
).
1
A layout is called ortho-45 if all geometrics are axis parallel or have slope ±1.
2
The L
∞
distance between two points p = (x
p
,y
p
) and q = (x
q
,y
q
) is the maximum of the horizontal and the vertical distance between
p and q i.e., d (p,q ) = max {|x
p
− x
q
|,|y
p
− y
q
|}.
3
There is a minor difference in the definition which we ignore in this paper (see [13]).
3
(a)
(b)
Figure 1:
The regions of influence of the core elements of a core segment.
Figure 2:
The L
∞
farthest Voronoi diagram of axis parallel segments.
Every point p along s is weighted with w (p ) = d (p, e
l
) = d (p, e
r
). The 45
◦
rays
4
emanating from the endpoints
of s partition the plane into the regions of influence of either the open core segment portion or the core
endpoints. Fig.1 illustrates the partitioning of space induced by a core segment in the L
∞
metric. Shaded
regions in Fig.1 are equidistant from both the core endpoint and the open core segment and can be assigned
arbitrarily to one of the two. In the region of influence of a core point p, distance is measured in the ordinary
weighted sense, that is, for any point t , d
w
(t , p) = d (t ,p ) + w (p). In the region of influence of an open core
segment s distance in essence is measured according to the farthest polygonal element defining s , that is,
d
w
(t , s ) = d (t ,e
l
) where e
l
is the polygonal element at the opposite side of the line through s than t . In
Fig.1, e
l
is indicated by arrows for different points. In L
∞
this is equivalent to the ordinary weighted distance
between t and s . The (weighted) bisector between two core elements can now be defined in the ordinary way,
always taking the weights of the core elements into consideration. Similarly the (weighted) Voronoi diagram
of a set of core elements can be defined as usual, using the definition given above, with the difference that
distance between a point t and a core element s is always measured in an additive weighted sense, d
w
(t , s ).
The (weighted) Voronoi diagram of core medial axis segments was first introduced in [16] as it provided a
solution to the critical area computation problem for a simpler notion of an open (called break) that was
based solely on geometric information. For Manhattan geometries, core segments are simple (additively
weighted) axis parallel line segments and points.
An important variation of Voronoi diagrams is the so called farthest Voronoi diagram. The farthest Voronoi
diagram of a set of polygonal sites is a partitioning of the plane into regions, such that the farthest Voronoi
region of a site s is the locus of points farther away from s than from any other site. For typical cases (e.g.
points, line segments) the farthest Voronoi diagram is a tree-like structure consisting only of unbounded
regions (see e.g. [3, 6, 15]). In the L
∞
metric, when sites are points or axis-parallel segments, the structure
of the L
∞
farthest Voronoi diagram is particularly simple, consisting always of exactly four regions. Figure 2
depicts the farthest Voronoi diagram of two sets of axis parallel segments. In both cases the farthest Voronoi
diagram consists of an axis parallel segment, shown in bold, (that can degenerate to a point) and four 45
◦
-
rays, shown as dashed bold rays, that together partition the plane into four regions (see [16]). In each region,
the L
∞
distance to the farthest element is measured as the vertical or horizontal distance to an axis parallel
line. In Figure 2 the axis parallel lines indicating farthest distance are depicted as dashed lines. The thin
arrows indicate the farthest L
∞
distance of selected points.
4
A 45
◦
ray is a ray of slope ±1.
4
(b)(a)
Figure 3:
(a) A net N spanning over two layers. (b) Dark defects create opens while transparent defects cause no faults.
3 A graph representation for nets
From a layout perspective a net N is a collection of interconnected shapes spanning over a number of layers.
The portion of N on a given layer A, N ∩ A, consists of a number of connected components. Every connected
component is a collection of overlapping polygons that can be unioned into a single shape (a simple one
or one with holes). Some of the shapes constituting net N are designated as terminal shapes representing
the entities that the net must interconnect. Terminal shapes typically consist of power buses (collection of
shapes representing VDD or GND), gates (intersections of PC and RX shapes), Sources and Drains of Transis-
tors (portions of RX shapes as obtained after subtracting regions overlapping with PC), and pins of macros.
Terminal shapes can also be user defined depending on user goals. A net remains functional as long as all
terminal shapes comprising the net remain interconnected. Otherwise the net is said to be broken. Fig. 3(a)
illustrates a simple net N spanning over two metal layers, say M1 and M2, where M2 is illustrated shaded. The
two contacts illustrated as black squares have been designated as terminal shapes. In Fig. 3(b), defects that
create opens are illustrated as dark squares and defects that cause no fault are illustrated hollow in dashed
lines. Note that hollow defects do break wires of layer M1, however, they do not create opens as no terminals
get disconnected.
We define a compact graph representation for N , denoted G (N ), as follows. There is a graph node for
every connected component of N on a conducting layer. A node containing terminal shapes is designated
as a terminal node. Two graph nodes are connected by an edge if and only if there exists at least one contact
or via connecting the respective components of N . To build G (N ) some net extraction capability needs to be
available. We assume that such capability exists. If not it is not hard to obtain one using a scan line approach
that detects intersections among shapes on same and neighboring layers and maintains nets using a union-
find data structure for efficiency. Net extraction is a well studied topic beyond the scope of this paper. For the
purposes of this paper we assume that G (N ) can be available for any net.
To perform critical area computation on a layer A we derive the extended graph of N on layer A, denoted
as G (N ,A), that can be obtained from G (N ) by expanding all components of N on layer A by their medial
axis. For every via or contact introduce an approximate point along the medial axis representing that via or
contact, referred to as a via-point, and a graph edge connecting the via-point with the node of the connecting
component of N. If a contact or via has been designated as terminal shape, designate also the corresponding
via point as terminal. In the presence of via clusters we can keep only one via point representing the entire
cluster. Any portion of the medial axis induced by edges of terminal shapes is also identified as terminal.
Fig. 4a illustrates G (N ,A), where A = M 1, for the net of Fig. 3. Terminal points are indicated by hollow circles.
Dashed lines represent the original M1 polygon and they are not part of G (N , A).
Given G (N , A) we can detect biconnected components, bridges and articulation points
5
using depth-first
search (DFS) as described in [10,27]. For our problem we only maintain some additional terminal information
to determine whether the removal of a vertex or edge actually breaks G (N ,A), i.e., whether it disconnects
G (N , A) leaving terminals in at least two different sides. For this purpose we chose the root of the DFS tree to
be a terminal node or terminal point and at every node i of the DFS tree we keep a flag indicating whether
the subtree rooted at i contains a terminal point. Any bridges or any articulation points whose removal does
not disconnect terminals of G (N ,A) are called trivial. Any biconnected component incident to only trivial
5
A biconnected component of a graph G is a maximal set of edges such that any two edges in the set lie on a common simple cycle.
An articulation point (resp. bridge) of G is a vertex (resp. edge) whose removal disconnects G .
5
