Proceedings ArticleDOI
On accurate modeling and efficient simulation of CMOS opens
C. Di,J.A.G. Jess +1 more
- pp 875-882
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TLDR
This paper presents a new modeling and simulation technique for CMOS opens that both the hazard and charge-sharing effects of all possible opens are modeled in terms of a set of detecting conditions that are efficiently represented at logic level.Abstract:
This paper presents a new modeling and simulation technique for CMOS opens. The significance of the method is that both the hazard and charge-sharing effects of all possible opens are modeled in terms of a set of detecting conditions. They are efficiently represented at logic level. Then during fault simulations only these detecting conditions are evaluated to decide if the opens are detected. In this way, all efficient simulation techniques developed at logic level can be applied. The paper shows how the detecting conditions are derived for arbitrary opens. Results of a parallel pattern simulator show a good trade-off of accuracy versus efficiency. >read more
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Cell-Aware Test
Friedrich Hapke,W. Redemund,A. Glowatz,Janusz Rajski,M. Reese,Marek Hustava,Martin Keim,Juergen Schloeffel,Anja Fast +8 more
TL;DR: The new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies, is described.
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A technique for logic fault diagnosis of interconnect open defects
TL;DR: The novel features of this work include a diagnostic fault model to capture potential faulty behaviors in the presence of an open defect and diagnosis algorithms that leverage the diagnostic model while circumventing the need for detailed circuit-level (SPICE) simulation and extraction of parasitic capacitance.
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Incremental fault diagnosis
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TL;DR: A model-free incremental diagnosis algorithm is outlined, which alleviates the need for an explicit fault model, and extensive results on combinational and full-scan sequential benchmark circuits confirm its resolution and performance.
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Finding defects with fault models
TL;DR: A process is presented to validate fault models used in fault diagnosis, which can be extended to test pattern generation and test quality estimation as well as fault diagnosis.
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Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs
TL;DR: The diagnosis techniques take the test-pattern sequence into account, and therefore, produce precise diagnosis results and the technique handles multiple faults of different fault models.
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A CMOS fault extractor for inductive fault analysis
F.J. Ferguson,John Paul Shen +1 more
TL;DR: This analysis shows that the traditional SSA fault model characterizes fewer than half of the faults extracted by FXT; graph-theoretic techniques provide little improvement in the percentage of realistic faults modeled.
Proceedings ArticleDOI
Testing oriented analysis of CMOS ICs with opens
Wojciech Maly,P. K. Nag,P. Nigh +2 more
TL;DR: It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open, and that the majority of opens which occur in CMOS static circuits manifest themselves as timing faults.
Proceedings ArticleDOI
Test Generation for MOS Circuits Using D-Algorithm
TL;DR: An application of the D-algorithm in generating tests for MOS circuit faults is described, which includes modeling and test generation for combinational and acyclic MOS circuits that may contain transmission gates and buses.