Open AccessBook
On-Chip Networks
TLDR
Various fundamental aspects of on-chip network design are examined and the reader is provided with an overview of the current state-of-the-art research in this field.Abstract:
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusionsread more
Citations
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Patent
System, method, and computer program product for improving memory systems
TL;DR: In this paper, a system, method, and computer program product for a memory system is described, which includes a first semiconductor platform including at least one first circuit, and at least two additional semiconductor platforms stacked with the first and additional circuits.
Proceedings ArticleDOI
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
TL;DR: This work designs a novel low-cost congestion propagation network that leverages both local and non-local network information for more accurate congestion estimates and offers effective adaptivity for congestion beyond neighboring nodes, and proposes Destination-Based Adaptive Routing (DBAR).
Journal ArticleDOI
How to Build a Beowulf: A Guide to the Implementation and Application of PC Clusters
TL;DR: This book provides an in-depth view of one possible Beowulf system covering details of hardware selection, operating system configuration, communication software and a parallel sorting application and basically fulfills the stated purpose, but the subject matter is too broad for a single book.
Proceedings ArticleDOI
Catnap: energy proportional multiple network-on-chip
TL;DR: The Catnap architecture, which consists of synergistic subnet selection and power-gating policies, is proposed which maximizes the number of consecutive idle cycles in a router, while avoiding performance loss due to overloading a subnet.
Book ChapterDOI
Input Versus Output Queueing on a SpaceDivision Packet Switch
TL;DR: Two simple models of queueing on an N ?? N space-division packet switch are examined, and it is possible to slightly increase utilization of the output trunks by dropping interfering packets at the end of each time slot, rather than storing them in the input queues.
References
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Proceedings ArticleDOI
The SPLASH-2 programs: characterization and methodological considerations
TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
Journal ArticleDOI
Networks on chips: a new SoC paradigm
Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Proceedings ArticleDOI
The PARSEC benchmark suite: characterization and architectural implications
TL;DR: This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs), and shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic.
Book
Principles and Practices of Interconnection Networks
William J. Dally,Brian Towles +1 more
TL;DR: This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies, allowing a designer to see all the steps of the process from abstract design to concrete implementation.
Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.