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Open AccessJournal ArticleDOI

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

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TLDR
A method is proposed that quantifies the slowdown that simultaneously-running tasks may experience due to collision in shared processor resources and is used to determine if a given MT processor is a good candidate for systems with timing requirements.
Abstract
Commercial Off-The-Shelf (COTS) processors are now commonly used in real-time embedded systems. The characteristics of these processors fulfill system requirements in terms of time-to-market, low cost, and high performance-per-watt ratio. However, multithreaded (MT) processors are still not widely used in real-time systems because the timing analysis is too complex. In MT processors, simultaneously-running tasks share and compete for processor resources, so the timing analysis has to estimate the possible impact that the inter-task interferences have on the execution time of the applications.In this paper, we propose a method that quantifies the slowdown that simultaneously-running tasks may experience due to collision in shared processor resources. To that end, we designed benchmarks that stress specific processor resources and we used them to (1) estimate the upper limit of a slowdown that simultaneously-running tasks may experience because of collision in different shared processor resources, and (2) quantify the sensitivity of time-critical applications to collision in these resources. We used the presented method to determine if a given MT processor is a good candidate for systems with timing requirements. We also present a case study in which the method is used to analyze three multithreaded architectures exhibiting different configurations of resource sharing. Finally, we show that measuring the slowdown that real applications experience when simultaneously-running with resource-stressing benchmarks is an important step in measurement-based timing analysis. This information is a base for incremental verification of MT COTS architectures.

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References
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The time-triggered architecture

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The Case of the Missing Supercomputer Performance: Achieving Optimal Performance on the 8,192 Processors of ASCI Q

TL;DR: This paper describes how to improved the effective performance of ASCI Q, the world's second-fastest supercomputer, to meet expectations and provides insight into performance analysis that is immediately applicable to other large-scale supercomputers.
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Transitioning from federated avionics architectures to Integrated Modular Avionics

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