On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments
Petar Radojković,Sylvain Girbal,Arnaud Grasset,Eduardo Quinones,Sami Yehia,Francisco J. Cazorla +5 more
- Vol. 8, Iss: 4, pp 34
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TLDR
A method is proposed that quantifies the slowdown that simultaneously-running tasks may experience due to collision in shared processor resources and is used to determine if a given MT processor is a good candidate for systems with timing requirements.Citations
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Real-time cache management framework for multi-core architectures
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Leveraging Multi-core Computing Architectures in Avionics
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Building timing predictable embedded systems
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Reliability challenges of real-time systems in forthcoming technology nodes
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References
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The worst-case execution-time problem—overview of methods and survey of tools
Reinhard Wilhelm,Jakob Engblom,Andreas Ermedahl,Niklas Holsti,Stephan Thesing,David Whalley,Guillem Bernat,Christian Ferdinand,Reinhold Heckmann,Tulika Mitra,Frank Mueller,Isabelle Puaut,Peter Puschner,Jan Staschulat,Per Stenström +14 more
TL;DR: Different approaches to the determination of upper bounds on execution times are described and several commercially available tools1 and research prototypes are surveyed.
Book
Programming with POSIX threads
TL;DR: This book offers an in-depth description of the IEEE operating system interface standard, POSIXAE (Portable Operating System Interface) threads, commonly called Pthreads, and explains basic concepts such as asynchronous programming, the lifecycle of a thread, and synchronization.
Proceedings ArticleDOI
The time-triggered architecture
TL;DR: An overview of the Time-Triggered Architecture is given, the architectural principles are discussed, the sensor/actuator interfaces in the TTA are described, the implementation of fault-tolerance is informed and the provision of fully specified interfaces between subsystems is described.
Proceedings ArticleDOI
The Case of the Missing Supercomputer Performance: Achieving Optimal Performance on the 8,192 Processors of ASCI Q
TL;DR: This paper describes how to improved the effective performance of ASCI Q, the world's second-fastest supercomputer, to meet expectations and provides insight into performance analysis that is immediately applicable to other large-scale supercomputers.
Proceedings ArticleDOI
Transitioning from federated avionics architectures to Integrated Modular Avionics
TL;DR: This paper identifies considerations for transitioning from a federated avionics architecture to an integrated modular avionics (IMA) architecture and addresses misconceptions about the resource management mechanisms that can occur during a transition to IMA.