Proceedings ArticleDOI
ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications
Akram Ben Ahmed,Kenichi Mori,Abderazek Ben Abdallah +2 more
- pp 257-262
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TLDR
An optimized version of the earlier design OASIS-2, called ONoC-SPL, that employs a Short-PassLink (SPL) customization which aims to reduce the communication latency for performance enhancement in data-intensive computation applications is presented.Abstract:
Network-on-Chip (NoC) has emerged as a promising paradigm to largely alleviate the limitations exhibited by the shared-bus based systems in current System-On-Chip (SoC) These problems include the lack of scalability, clock skew, lack of support for concurrent communication, and increasing power consumption Based upon a packet/flit switching scheme, NoC allows a concurrent transmission of data providing a higher bandwidth and performanceread more
Citations
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Journal ArticleDOI
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
TL;DR: An efficient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance of 3D-NoC systems while ensuring fault-Tolerance.
Journal ArticleDOI
Unified multi-objective mapping and architecture customisation of networks-on-chip
TL;DR: A methodology for multi-objective optimisation of NoC standard architectures using Genetic Algorithms is presented and shows that the architectures generated by the methodology outperform those of other standard architecture customisation techniques with respect to four metrics: power, area, delay and reliability, and their combination.
Book
Multicore systems-on-chip:practical hardware/software design
TL;DR: This paper presents a case study of the design of the dual-Execution Processor Architecture for Embedded Multicore SoC, and discusses power optimization techniques used in this architecture.
Proceedings ArticleDOI
Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems
TL;DR: Evaluation results show that the proposed 3D-FTO is able to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient.
Proceedings ArticleDOI
Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era
TL;DR: This work proposes an efficient design method for Network-on-Chip architecture based on a novel run-time monitoring mechanism (RMM) that allows to easily compute optimal architecture hardware parameters (i.e Buffer size) and allocate the appropriate values on demand to satisfy the requirements of any given application.
References
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Proceedings ArticleDOI
A network on chip architecture and design methodology
Shashi Kumar,Axel Jantsch,Juha-Pekka Soininen,Martti Forsell,Mikael Millberg,Johnny Öberg,Kari Tiensyrjä,Ahmed Hemani +7 more
TL;DR: A packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources which is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack.
Journal ArticleDOI
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
TL;DR: This paper develops a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures and explores design trade-offs that characterize the NoC approach and obtains comparative results for a number of common NoC topologies.
Journal ArticleDOI
The Torus Routing Chip
TL;DR: The torus routing chip (TRC) is a selftimed chip that performs deadlock-free cut-through routing ink-aryn-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels.
Journal ArticleDOI
QNoC: QoS architecture and design process for network on chip
TL;DR: A customized Quality-of-Service NoC (QNoC) architecture is derived by modifying a generic network architecture which minimizes the network cost while maintaining the required QoS.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.