Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
- pp 914-919
TLDR
SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.Abstract:
Increasing communication demands of processor and memory cores in Systems on Chips (SoCs) necessitate the use of Networks on Chip (NoC) to interconnect the cores. An important phase in the design of NoCs is he mapping of cores onto the most suitable opology for a given application. In this paper, we present SUNMAP a tool for automatically selecting he best topology for a given application and producing a mapping of cores onto that topology. SUNMAP explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints. The tool supports different routing functions (dimension ordered, minimum-path, traffic splitting) and uses floorplanning information early in the topology selection process to provide feasible mappings. The network components of the chosen NoC are automatically generated using cycle-accurate SystemC soft macros from X-pipes architecture. SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs. Several experimental case studies are presented in the paper, which show the rich design space exploration capabilities of SUNMAP.read more
Citations
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Journal ArticleDOI
A survey of research and practices of Network-on-chip
TL;DR: The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Journal ArticleDOI
"It's a small world after all": NoC performance optimization via long-range link insertion
Umit Y. Ogras,Radu Marculescu +1 more
TL;DR: A methodology to automatically synthesize an architecture which is neither regular nor fully customized which demonstrates a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.
Proceedings ArticleDOI
Key research problems in NoC design: a holistic perspective
TL;DR: A general description for NoC architectures and applications is provided and several outstanding research problems are enumerated organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization.
Journal ArticleDOI
A survey on application mapping strategies for Network-on-Chip design
TL;DR: A detailed survey of the work done in last one decade in the domain of application mapping is presented, apart from classifying the reported techniques, it also performs a quantitative comparison among them.
References
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Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
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The future of wires
R. Ho,Ken Mai,Mark Horowitz +2 more
TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Proceedings ArticleDOI
A network on chip architecture and design methodology
Shashi Kumar,Axel Jantsch,Juha-Pekka Soininen,Martti Forsell,Mikael Millberg,Johnny Öberg,Kari Tiensyrjä,Ahmed Hemani +7 more
TL;DR: A packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources which is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack.
Proceedings ArticleDOI
A generic architecture for on-chip packet-switched interconnections
Pierre Guerrier,Alain Greiner +1 more
TL;DR: This paper presents an architectural study of a scalable system-level interconnection template, and discusses the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services.
Book
Algorithms for VLSI Physical Design Automation
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.