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Proceedings ArticleDOI

Parallel global routing algorithms for standard cells

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TLDR
Three different parallel algorithms based on a state-of-the-art global router called TimberWolfSC, implemented by using the Message Passing Interface, are proposed, and evaluated on a wide range of parallel platforms such as the Sun SparcCenter 1000 and the Intel Paragon.
Abstract
In this paper, we propose three different parallel algorithms based on a state-of-the-art global router called TimberWolfSC. The parallel algorithms have been implemented by using the Message Passing Interface (MPI), and have been evaluated on a wide range of parallel platforms such as the Sun SparcCenter 1000 and the Intel Paragon. Our experimental results show good speedups and qualities from two of these parallel algorithms. We have been able to reduce runtimes of some circuits from half an hour to 5 minutes, obtained speedups of about 4.0 to 5.0 on 8 processors, with less than 2-3% degradation of quality of the solutions.

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Citations
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Journal ArticleDOI

Distributed-memory parallel routing for field-programmable gate arrays

TL;DR: This paper shows that the negotiation-based routing paradigm, which has been applied successfully in several FPGA routers, can be parallelized to achieve increased performance without any significant decrease in the quality of the results.
Book ChapterDOI

TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs

TL;DR: A distributed-memory parallel routing algorithm for FPGAs based on the partitioning of the routing graph under special FPGA architectural constraints is proposed that can achieve linear and superlinear speedups in relation to the state-of-art VPR router.
Journal ArticleDOI

Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation

TL;DR: This paper parallelizes the Pathfinder global routing algorithm -a widely used FPGA routing algorithm- for running on multi-core systems to improve runtime of routing process.
Proceedings ArticleDOI

A parallel algorithm for timing-driven global routing for standard cells

TL;DR: By integrating high performance interconnection tree construction, wire-sizing, and switch-able segment channel optimization together, an adaptive timing-driven global routing algorithm which minimizes the timing delay as well as circuit area is proposed.

Novel algorithms for placement and routing and their parallel implementations

TL;DR: A fast and effective module placement algorithm which is based on the PROUD algorithm and a parallel version of the modified algorithm that combines both fine grain and coarse grain parallelism to obtain another order of magnitude improvement in the runtime with very little loss of the quality of the layout.
References
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Book

An introduction to parallel algorithms

TL;DR: This book provides an introduction to the design and analysis of parallel algorithms, with the emphasis on the application of the PRAM model of parallel computation, with all its variants, to algorithm analysis.
Journal ArticleDOI

An Algorithm for Path Connections and Its Applications

TL;DR: The algorithm described in this paper is the outcome of an endeavor to answer the following question: Is it possible to find procedures which would enable a computer to solve efficiently path-connection problems inherent in logical drawing, wiring diagramming, and optimal route finding?
Book

Introduction to parallel computing: design and analysis of algorithms

TL;DR: Performance and Scalability of Parallel Systems, General Issues in Mapping Systolic Systems Onto Parallel Computers, and Speedup Anomalies in Parallel Search Algorithms.
Journal ArticleDOI

Hierarchical Wire Routing

TL;DR: A new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels and is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.
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