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Patent

Phase change memory bits reset through a series of pulses of increasing amplitude

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TLDR
In this paper, a set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude, and a check determines whether the bit has been reset.
Abstract
A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

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Citations
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Phase change memory cell and manufacturing method

TL;DR: A phase change memory cell includes first and second electrodes electrically coupled by a phase change element as discussed by the authors, which can transition from crystalline to amorphous states at a lower temperature than the higher reset transition temperature.
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References
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Patent

Method and system to store information

TL;DR: In this article, a method and system to program a memory material is described, which may include applying three signals having different durations and different amplitudes to the memory material to program it to a predetermined state.
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Set programming methods and write driver circuits for a phase-change memory array

TL;DR: In this article, a set-programming method for a phase-change memory array is described, where the set current pulse is applied to phase change cells to transition to the set resistance state.
Patent

Phase change memory device

TL;DR: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a number of address lines connected to the cells; a write stage and a reading stage connected to an array as discussed by the authors.
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Flash memory having adaptive sensing and method

TL;DR: In this article, the reference value is derived by on-chip programmed and erased cells, and it can automatically adapt to changes in the fabrication process, temperature, operating voltages and the like.
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Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations

TL;DR: In this article, a nonvolatile memory device is described comprising a memory array, a row decoder and a column selector for addressing the memory cells of the memory array and a biasing stage for biasing the array access device terminal of the addressed memory cell.
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