Journal ArticleDOI
Power analysis and minimization techniques for embedded DSP software
TLDR
In this article, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements, and a scheduling technique based on the new instruction level power model is proposed.Abstract:Â
Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged.read more
Citations
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Journal ArticleDOI
System-level power optimization: techniques and tools
Luca Benini,Giovanni De Micheli +1 more
TL;DR: This tutorial presents a cohesive view of power-conscious system-level design, which considers systems as consisting of a hardware platform executing software programs, and considers the major constituents of systems: processors, memories and communication resources.
Journal ArticleDOI
An optimal memory allocation scheme for scratch-pad-based embedded systems
TL;DR: This article presents a compiler strategy that automatically partitions the data among the memory units, and shows that this strategy is optimal, relative to the profile run, among all static partitions for global and stack data.
Proceedings ArticleDOI
Power optimization of variable voltage core-based systems
TL;DR: The design methodology for the low power core-based real-time system-on-chip based on dynamically variable voltage hardware is developed, with the highlight of the proposed approach the non-preemptive scheduling heuristic which results in solutions very close to optimal ones for many test cases.
Journal ArticleDOI
Power optimization of variable-voltage core-based systems
TL;DR: This work developed the design methodology for the low-power core-based real-time SOC based on dynamically variable voltage hardware and proposes a nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases.
Proceedings ArticleDOI
Run-time power estimation in high performance microprocessors
Russ Joseph,Margaret Martonosi +1 more
TL;DR: In this paper, the authors examine the use of hardware performance counters as proxies for power meters, and discuss which performance counters count power-relevant events, and how to estimate event counts for powerrelevant events not well supported by current, commonly available performance counters.
References
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Power analysis of embedded software: a first step towards software power minimization
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Saving power in the control path of embedded processors
TL;DR: The authors' two-pronged attack uses Gray code addressing and cold scheduling to eliminate bit switches to save power in embedded processors.