Journal ArticleDOI
PowerPC 601 and Alpha 21064: a tale of two RISCs
James E. Smith,Shlomo Weiss +1 more
TLDR
A discussion is given on two RISC implementations: from Digital Equipment Corporation, the Alpha 21064, and from IBM/Motorola/Apple, the PowerPC 601; both are superscalar implementations, that is, they can sustain execution of two or more instructions per clock cycle.Abstract:
A discussion is given on two RISC implementations: from Digital Equipment Corporation, the Alpha 21064, and from IBM/Motorola/Apple, the PowerPC 601. Both are superscalar implementations, that is, they can sustain execution of two or more instructions per clock cycle. Otherwise, these two implementations present vastly different philosophies for achieving high performance. The PowerPC 601 focuses on powerful instructions and great flexibility in processing order, while the Alpha 21064 depends on a very fast clock, with simpler instructions and a more streamlined implementation structure. These two RISC microprocessors exemplify contrasting, but equally valid, implementation philosophies. An overview is given of the instruction sets and the authors emphasize the differences in design: PowerPC uses powerful instructions so that fewer are needed to get the job done; Alpha uses simple instructions so that the hardware can be kept simpler and faster. The authors also discuss the pipelined implementations of the two architectures; again, the contrast is between powerful and simple. >read more
Citations
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Journal ArticleDOI
Trace-driven memory simulation: a survey
Richard Uhlig,Trevor Mudge +1 more
TL;DR: A survey and analysis of trace-driven memory simulation tools can be found in this article, where the authors discuss the strengths and weaknesses of different approaches and show that no single method is best when all criteria, including accuracy, speed, memory, flexibility, portability, expense, and ease of use are considered.
Proceedings ArticleDOI
Reducing register ports for higher speed and lower energy
TL;DR: This work proposes to reduce the number of register ports through two proposals, one for reads and the other for writes, and uses decoupled rename, a technique which separates dependence and physical tagging of register operands.
Patent
Apparatus for randomly sampling instructions in a processor pipeline
George Z. Chrysos,Jeffrey Dean,James W. Hicks,Daniel L. Leibholz,Edward J. Mclellan,Carl A. Waldspurger,William E. Weihl +6 more
TL;DR: In this paper, an apparatus is provided for sampling instructions in a processor pipeline of a system, where instructions are identified and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline.
Proceedings ArticleDOI
Efficient memory simulation in SimICS
Peter S. Magnusson,Bengt Werner +1 more
TL;DR: Novel techniques used for efficient simulation of memory in SimICS; an instruction level simulator developed at SICS are described, a memory simulation scheme that supports a range of features for use in computer architecture research, program profiling, and debugging.
Real-Time Optical Flow
TL;DR: This thesis describes a space-time tradeoff to this algorithm which converts a quadratic-time algorithm into a linear-time one, as well as a method for dealing with the resulting problem of temporal aliasing.
References
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Reduced instruction set computers
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Journal ArticleDOI
A 200-MHz 64-b dual-issue CMOS microprocessor
Daniel W. Dobberpuhl,R. Witek,R. Allmon,R. Anglin,D. Bertucci,S.M. Britton,L. Chao,R.A. Conrad,D.E. Dever,B. Gieseke,Soha Hassoun,G. Hoeppner,K. Kuchler,M. Ladd,B.M. Leary,L. Madden,Edward J. McLellan,D.R. Meyer,J. Montanaro,Donald A. Priore,V. Rajagopalan,S. Samudrala,S. Santhanam +22 more
TL;DR: A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations.
Book
The PowerPC Architecture: A Specification for a New Family of RISC Processors
TL;DR: The PowerPC Architecture is a must for anyone who needs to understand the levels of compatibility between different processors in the PowerPC family-the 601 microprocessor, the 603 (low-end, battery-powered requirements), 604 (optimized price/performance for scaleable symmetric multiprocessors), and the 620 (for high-end technical and commercial requirements about performance).
Journal ArticleDOI
The Alpha AXP architecture and 21064 processor
TL;DR: The Alpha AXP 64-b architecture, which forms the basis for a series of high-performance computer systems, is described and performance measurement results for a variety of commonly used benchmarks under both OpenVMS AXP V1 and DEC OSF/1 V1.2 are presented.
Journal ArticleDOI
The Power PC 601 microprocessor
TL;DR: The PowerPC 601 microprocessor, the first of a family of processors based on the PowerPC architecture, is described, which contains a 32-Kb cache and a superscalar machine organization that allows dispatch and execution of up to three instructions each clock cycle.