Journal ArticleDOI
Built-In Self-Test Techniques
TLDR
The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.Abstract:
A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.read more
Citations
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Book
The Test Access Port and Boundary Scan Architecture
Colin Maunder,Rodham E. Tulloss +1 more
TL;DR: In this article, a wheel decorating ornament comprising an annular, planar sheet of material decorated on opposite sides, axially disposed between the groups of spokes and radially disposed at the rim and the hub, is presented.
Journal ArticleDOI
Cellular automata-based pseudorandom number generators for built-in self-test
TL;DR: The cellular automata-logic-block-observation circuits presented are expected to improve upon conventional design for testability circuitry such as built-in logic-block operation as a direct consequence of reduced cross correlation between the bit streams that are used as inputs to the logic unit under test.
Proceedings ArticleDOI
Logic BIST for large industrial designs: real issues and case studies
TL;DR: The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.
Journal ArticleDOI
A tutorial on built-in self-test. I. Principles
TL;DR: An overview of built-in self-test (BIST) principles and practices is presented, and Linear feedback shift register theory is reviewed.
Journal ArticleDOI
Circular self-test path: a low-cost BIST technique for VLSI circuits
Andrzej Krasniewski,S. Pilarski +1 more
TL;DR: Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test.
References
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Journal ArticleDOI
Random Pattern Testability
TL;DR: A new analytical method of computing the fault coverage that is fast compared with simulation is described that is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault Coverage of the random test.
Journal ArticleDOI
Design for Autonomous Test
McCluskey,Bozorgui-Nesbat +1 more
TL;DR: A technique for modifying networks so that they are capable of self test is presented, partitioning the network into subnets with sufficiently few inputs that exhaustive testing of the subnetworks is possible.
Journal ArticleDOI
Verification Testing—A Pseudoexhaustive Test Technique
TL;DR: A new approach to test pattern generation which is particularly suitable for self-test is described, which requires much less computation time and fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected.
Journal ArticleDOI
Syndrome-Testable Design of Combinational Circuits
TL;DR: This paper focuses on classical testing of combinational circuits and the large storage requirement for a list of the fault-free response of the circuit to the test set.
Journal ArticleDOI
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
E. B. Eichelberger,E. Lindbloom +1 more
TL;DR: Embedded linear feedback shift registers can be used for logic component self-test and a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis is given.