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Proceedings ArticleDOI

ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications

TLDR
The ReCoM architecture is described and its effectiveness for a digital signal processing benchmark application and its efficient configuration and data memory architecture is presented.
Abstract
Reconfigurable mixed grain (ReCoM) is a novel reconfigurable compute fabric (RCF) architecture based on a mixed-grain reconfigurable array which combines a RISC microprocessor and a reconfigurable hardware for computation-intensive applications. ReCoM comprises a modified RISC microprocessor, a dynamically reconfigurable processing array including reconfigurable cells formed by a 64-bits ALU, look up tables (LUTs), word-level arithmetic units, and an efficient configuration and data memory architecture. This paper describes the ReCoM architecture and presents its effectiveness for a digital signal processing benchmark application

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Citations
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Proceedings ArticleDOI

RoSA: a reconfigurable stream-based architecture

TL;DR: RoSA, a coarse-grained reconfigurable architecture that combines compilation techniques and hardware reuse to accelerate the execution of stream-based applications, is presented.
Proceedings ArticleDOI

Two-level configuration for FPGA: A new design methodology based on a computing fabric

TL;DR: A new methodology based on two configuration levels that enables the fast implementation of data processing algorithms by people who are not experts in FPGA design, while achieving higher performances than a pure software solution is presented.
Proceedings ArticleDOI

An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture

TL;DR: The experimental results gathered through an accurate simulation model of ReCoM show performance figures encouragingly better than other DSP or alternative reconfigurable systems and demonstrate that Re coCoM is very scalable and it successfully extracts the parallelism from streamed applications.
Proceedings ArticleDOI

A new RC design for mixed-grain based dynamically reconfigurable architectures

TL;DR: This paper presents the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture that delivers a gate-level implementation of the Reconfigured Logic Unit (RLU) focusing on the ALU implementation.
Proceedings ArticleDOI

Research and design of reconfigurable 64-bit ALU

TL;DR: The logic design of ALU, an important constituent part of CPU, is described, which reduces the size of project effectively, accordingly improves the performance of the ALU and effectively combines the design idea of two-bit-in-one-group and conditional sum.
References
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Proceedings ArticleDOI

Garp: a MIPS processor with a reconfigurable coprocessor

TL;DR: Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Journal ArticleDOI

MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

TL;DR: The MorphoSys architecture is described, including the reconfigurable processor array, the control processor, and data and configuration memories, and the suitability of MorphoSy for the target application domain is illustrated with examples such as video compression, data encryption and target recognition.
Proceedings Article

MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources

Ethan Mirsky, +1 more
TL;DR: MATRIX as discussed by the authors is a coarse-grained, reconfigurable com- puting architecture which supports confgurable instruction distribution, where device resources are allocated to control- ling and describing the computation on a per task basis.
Proceedings ArticleDOI

MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources

Mirsky, +1 more
TL;DR: MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports configurable instruction distribution that can serve as an instruction store, a memory element, or a computational element, and the adaptability is made possible by a multi-level configuration scheme.

A First Generation DPGA implementation

E. Tau
TL;DR: This minimal, first generation DPGA uses traditional 4-LUTs for the basic array element, but backs LUT and interconnect programming cells with a 4-context memory implemented using dynamic RAM.