Proceedings ArticleDOI
Reversible cryptographic hardware with optimized quantum cost and delay
Anindita Banerjee
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TLDR
Novel designs for reversible ALU of a cryptoprocessor which have been implemented in standard gate library are proposed and the quantum cost reported here are better than the lower bounds reported in literature.Abstract:
In order to defend the power analysis attack reversible logic is a good candidate as it ideally does not dissipate any heat and today reversible logic is an emerging research area. In literature different designs for reversible hardware cryptography have been proposed but they have been implemented using complex gate libraries and further theorems have been proposed defining lower limit of implementation cost which is quantum cost. We have proposed novel designs for reversible ALU of a cryptoprocessor which have been implemented in standard gate library and the quantum cost reported here are better than the lower bounds reported in literature. Further we have calculated delay of the proposed designs. We have verified that our proposed designs are minimal with respect to gate count which is circuit cost by simulating it in RevKit. This is for the first time that the optimization algorithms to optimize quantum cost and delay have been applied to improvise on the cost metric in reversible ALU design.read more
Citations
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Journal ArticleDOI
Optimised reversible divider circuit
Ali Bolhassani,Majid Haghparast +1 more
TL;DR: The comparative results show that the proposed designs individually have less hardware complexity, garbage outputs, constant inputs, quantum cost and significantly better scalability than the existing works.
Proceedings ArticleDOI
Encryption using reconfigurable reversible logic gate and its simulation in FPGAs
TL;DR: A complete scheme for encryption/decryption of 8-bit data is described using VHDL language and its quantum cost is calculated and its reconfigurable reversible gate is presented.
Design of Reversible Logic ALU using Reversible logic gates with Low Delay Profile
TL;DR: The design of 1-bit reversible ALU using reversible logic gates is proposed and the proposed design is analyzed on FPGA SPARTAN6 device and is compared in terms of propagation delay, quantum cost and garbage outputs.
Proceedings ArticleDOI
Novel algorithm for symmetric encryption
A. Skorupski,K. Gracki +1 more
TL;DR: The paper presents a new algorithm for block cipher with symmetric encryption and decryption algorithm based on reversible logic that allows to build a cipher with one FPGA chip.
References
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