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Open AccessJournal Article

Reversible logic

W.D. Pan, +1 more
- 01 Feb 2005 - 
TLDR
The inputs and outputs of reversible logic gates can be uniquely retrievable from each other, which makes them very attractive for applications where extremely low power consumption, or heat dissipation, is desirable.
Abstract
This work presents the logical reversibility. The inputs and outputs of reversible logic gates can be uniquely retrievable from each other. The reversible logic operations can't erase information and dissipate zero heat. The circuit actually operates in a backward operation, allows reproducing the inputs from the outputs and consumes zero power. As the basic elements of any logic circuit, logic gates are used to realize Boolean functions. By combining reversible logic gates, reversible circuits can perform complex logical and arithmetic operations. A one-to-one mapping between inputs and outputs is realized. The logical operations run backwards by cascading a reversible logic gate with its dual (inverse). Reversible circuits are also called lossless circuits, as there is neither energy loss nor information loss. These circuits are very attractive for applications where extremely low power consumption, or heat dissipation, is desirable in areas ranging from communications, low power VLSI (very large-scale integration) technology, optical computing to nanotechnology. Reversible logic found to be very useful in quantum computing where the quantum evolution is inherently reversible.

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Citations
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Journal ArticleDOI

A Novel Reversible BCD Adder For Nanotechnology Based Systems

TL;DR: It is shown that the proposed reversible BCD adder has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and garbage outputs with compared to the existing counterparts.

Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology

TL;DR: A novel 4x4 bit reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers and can be generalized for NxN bit multiplication.
Journal ArticleDOI

Optimized reversible multiplier circuit

TL;DR: Two new 4 × 4 bit reversible multiplier designs are presented which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers.
Journal ArticleDOI

A Novel Fault Tolerant Reversible Gate For Nanotechnology Based Systems

TL;DR: The proposed parity preserving reversible gate, NFT, allows any fault that affects no more than a single signal to be detectable at the circuit's primary outputs, and it is shown that the NFT gate can implement all Boolean functions.

Novel Reversible Multiplier Circuit in Nanotechnology

TL;DR: In this paper, the authors proposed a 4x4 bit reversible multiplier circuit, which is faster and has lower hardware complexity compared to the existing designs in terms of number of gates and number of garbage outputs.
References
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Journal ArticleDOI

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Journal ArticleDOI

Synthesis of reversible logic circuits

TL;DR: In an application important to quantum computing, the synthesis of oracle circuits for Grover's search algorithm are synthesized, and a significant improvement over a previously proposed synthesis algorithm is shown.
Journal ArticleDOI

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TL;DR: The history of the thermodynamics of information processing, beginning with the paradox of Maxwelrs demon, is reviewed, continuing through the efforts of Szilard, Brillouin, and others to demonstrate a thermodynamic cost of information acquisition, and a brief survey of recent work on quantum reversible computation is surveyed.
Journal ArticleDOI

Reversible cascades with minimal garbage

TL;DR: It is shown that any Boolean function can be realized as a reversible network in terms of this new approach by giving the theoretical method of finding such a network.
Proceedings ArticleDOI

Efficient adder circuits based on a conservative reversible logic gate

TL;DR: Novel full adder circuits using Fredkin gates are proposed which have lower hardware complexity than the current state-of-the-art, while generating the additional signals required for carry skip adder architectures.