Proceedings ArticleDOI
RTL fault modeling
M. Karunaratne,A. Sagahayroon,S. Prodhuturi +2 more
- pp 1717-1720
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TLDR
The experimental results presented in this paper indicate that fault coverage obtained using RTL level fault modeling has resulted in a coverage that is in close proximity with the corresponding gate-level fault coverage.Abstract:
Testing of digital circuits has traditionally been done using fault models at the gate level or below. Use of these lower level fault models adds complexity and delays testing efforts to later in the design cycle. There is a need to develop a design methodology for performing fault simulation throughout the design process, at many levels of abstraction. This work focuses on fault modeling and simulation at the register transfer (RT) level, and aims at exploring the capabilities of the stuck-at fault model in computing the fault coverage at the RT-level. The experimental results presented in this paper indicate that fault coverage obtained using RTL level fault modeling has resulted in a coverage that is in close proximity with the corresponding gate-level fault coverageread more
Citations
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Proceedings ArticleDOI
Efficient RTL Coverage Metric for Functional Test Selection
TL;DR: A new input/output transition fault-coverage metric (TRIO) at the register-transfer level is shown to perform much better than current metric in test selection at only an incrementally higher computational cost.
Journal ArticleDOI
Automation of Test Program Synthesis for Processor Post-silicon Validation
TL;DR: A greed-based strategy, where the instruction sequences that detect the freshly identified faults are preserved throughout the evolutionary process to identify the hard-to-test faults of the processor and the overall coverage is improved.
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SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
TL;DR: In this paper, the authors propose an automated CAD framework called SAF to identify an SoC's security assets at the register transfer level (RTL) through comprehensive vulnerability analysis under different threat models.
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Partial state monitoring for fault detection estimation
TL;DR: A new type of hardware monitor is proposed for the probabilistic determination of how many times a fault was likely to have been covered during functional test or program execution, which has the potential to provide new dynamic optimization capabilities for on-chip field testing.
Proceedings ArticleDOI
Beyond test pattern generation: Coverage analysis
TL;DR: A high level design verification scheme for the circuits designed at the behavioral level based on selection of a goal node in a control flow graph representation of a design under test which establishes the fact that high code coverage guarantees quality circuit design.
References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Proceedings ArticleDOI
An observability-based code coverage metric for functional simulation
TL;DR: A new metric for measuring the extent of design verification provided by a set of functional simulation vectors is proposed, which can be used uniformly for all designs and computes observability information to determine whether effects of errors that are activated by the program stimuli can be observed at the circuit outputs.
Proceedings ArticleDOI
An RT-level fault model with high gate level correlation
TL;DR: This paper aims at exploiting the capabilities of VHDL simulators to compute faulty responses at the RT-level, and shows that simulation of a faulty circuit is no more costly than simulation of the original circuit.
Proceedings ArticleDOI
Improving gate level fault coverage by RTL fault grading
Weiwei Mao,R.K. Gulati +1 more
TL;DR: Experimental results show that RTL fault coverage is quite close to fault coverage achieved at the gate level when designs are completed and mapped to a technology library and effort to improve fault coverage at the RTL level very likely results in corresponding improvement of fault Coverage at the Gate level.
Proceedings ArticleDOI
Behavioral fault modeling in a VHDL synthesis environment
Ronald J. Hayne,B.W. Johnson +1 more
TL;DR: New fault models for VHDL behavioral descriptions of combinational logic circuits developed via abstraction of industry standard single-stuck-line faults into the behavioral domain provide improved fault coverage over previous fault models.