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Open AccessJournal ArticleDOI

Runtime instrumentation of SystemC/TLM2 interfaces for fault tolerance requirements verification in software cosimulation

TLDR
A SystemC transaction level modelling wrapping library that can be used for the assertion of system properties, protocol compliance, or fault injection and has been successfully applied to the robustness verification of the on-board boot software of the Instrument Control Unit of the Solar Orbiter's Energetic Particle Detector.
Abstract
This paper presents the design of a SystemC transaction level modelling wrapping library that can be used for the assertion of system properties, protocol compliance, or fault injection. The library uses C++ virtual table hooks as a dynamic binary instrumentation technique to inline wrappers in the TLM2 transaction path. This technique can be applied after the elaboration phase and needs neither source code modifications nor recompilation of the top level SystemC modules. The proposed technique has been successfully applied to the robustness verification of the on-board boot software of the Instrument Control Unit of the Solar Orbiter's Energetic Particle Detector.

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Proceedings ArticleDOI

Fault-effect analysis on system-level hardware modeling using virtual prototypes

TL;DR: An efficient approach to verify or falsify failures detected with VP fault simulation and the exclusion of incorrect faults from fault-effect analyses further improves the accuracy and efficiency of fault-injection campaigns.
References
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Journal ArticleDOI

Design and verification of SystemC transaction-level models

TL;DR: This paper presents an approach to design and verify SystemC models at the transaction level and presents a genetic algorithm to enhance the assertions coverage and ensures the soundness of the approach by proving the correctness of the SystemC-to-AsmL and AsmL- to-SystemC transformations.
Journal ArticleDOI

Two challenges in embedded systems design: predictability and robustness.

TL;DR: I discuss two main challenges in embedded systems design: the challenge to build predictable systems, and that to build robust systems and suggest how predictability can be formalized as a form of determinism, and robustness as a forms of continuity.
Proceedings ArticleDOI

Implementation of a Transaction Level Assertion Framework in SystemC

TL;DR: In this paper, the authors present a prototype implementation of a TL assertion framework using SystemC, which is currently the de facto standard for system modeling and is used for verification of transaction level models.
Journal ArticleDOI

A Tractable and Fast Method for Monitoring SystemC TLM Specifications

TL;DR: This work addresses assertion-based verification (ABV) of TLM systemC models, and proposes a framework for supervising during simulation the verification of temporal properties expressed in PSL.

Assertion-Based Verification of Transaction Level Models.

TL;DR: A novel methodology to apply AssertionBased Verification to Transaction Level Models based on using Aspect-Oriented Programming techniques and mapping of transactions to Boolean signals and automatic event clock creation enables the concise formulation of assertions.