Patent
Semiconductor device and method of manufacturing same
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TLDR
In this article, a patterned resist (25 ) is formed so as to cover a low voltage operation region (A 2 ), a second LDD implantation process of implanting an impurity ion ( 14 ) by using the resist ( 25 ) as a mask, is performed over a silicon oxide film ( 6 ) thereby to form an impurate diffusion region ( 13 ) in the surface of a semiconductor substrate ( 1 ) in a high voltage operation regions (A 1 ).Abstract:
Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist ( 25 ) is formed so as to cover a low voltage operation region (A 2 ), a second LDD implantation process of implanting an impurity ion ( 14 ) by using the resist ( 25 ) as a mask, is performed over a silicon oxide film ( 6 ) thereby to form an impurity diffusion region ( 13 ) in the surface of a semiconductor substrate ( 1 ) in a high voltage operation region (A 1 ). After this step, the silicon oxide film ( 6 ) in the high voltage operation region (A 1 ) contains the impurity during the second LDD implantation process whereas the silicon oxide film ( 6 ) in a low voltage operation region (A 2 ) contains no impurity. This leads to such a characteristic that in the following pre-treatment with a wet process, the silicon oxide film ( 6 ) containing the impurity in the high voltage operation region (A 1 ) is reduced in thickness, and the silicon oxide film ( 6 ) containing no impurity in the low voltage operation region (A 2 ) is not reduced in thickness.read more
Citations
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References
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