J
Joseph M. Steigerwald
Researcher at Intel
Publications - 28
Citations - 929
Joseph M. Steigerwald is an academic researcher from Intel. The author has contributed to research in topics: Layer (electronics) & Electrode. The author has an hindex of 12, co-authored 28 publications receiving 906 citations. Previous affiliations of Joseph M. Steigerwald include Sony Broadcast & Professional Research Laboratories.
Papers
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Proceedings ArticleDOI
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai,C. Auth,Sridhar Balakrishnan,M. Bost,Ruth A. Brain,V. Chikarmane,R. Heussner,Makarem A. Hussein,Jack Hwang,D. Ingerly,R. James,J. Jeong,C. Kenyon,E. Lee,Seung Hwan Lee,Nick Lindert,Mark Y. Liu,Z. Ma,T. Marieb,Anand Portland Murthy,Ramune Nagisetty,Sanjay Natarajan,J. Neirynck,Andrew Ott,C. Parker,J. Sebastian,R. Shaheed,Swaminathan Sivakumar,Joseph M. Steigerwald,S. Tyagi,Cory E. Weber,Bruce Woolery,Yeoh Andrew W,Kevin Zhang,M. Bohr +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Patent
Self-aligned contacts
T Bohr Mark,Tahir Ghani,Nadia M. Rahhal-Orabi,Joshi Subhash,Joseph M. Steigerwald,Jason Klaus,Jack Hwang,Mackiewicz Ryan +7 more
TL;DR: In this article, the insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations, and a pair of diffusion regions adjacent to the pair of spacers.
Proceedings ArticleDOI
A high performance 180 nm generation logic technology
Simon Yang,S. Ahmed,B. Arcot,R. Arghavani,P. Bai,S. Chambers,P. Charvat,Raymond E. Cotner,R. Gasser,Tahir Ghani,Makarem A. Hussein,Chia-Hong Jan,C. Kardas,J. Maiz,P. McGregor,B. McIntyre,P. Nguyen,Paul A. Packan,Ian R. Post,Swaminathan Sivakumar,Joseph M. Steigerwald,M. Taylor,B. Tufts,S. Tyagi,M. Bohr +24 more
TL;DR: In this article, a 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low/spl epsi/ SiOF dielectrics.
Patent
Polish to remove topography in sacrificial gate layer prior to gate patterning
TL;DR: In this article, the authors describe techniques for fabricating FinFET transistors (e.g., double-gate, trigate, etc) that enable subsequent gate patterning and sacrificial gate material opening via polishing.
Patent
Wrap-around trench contact structure and methods of fabrication
TL;DR: In this article, a wrap-around source/drain trench contact structure is described, where a plurality of semiconductor fins extend from a semiconductor substrate, and a channel region is disposed in each fin between a pair of source/drain regions.