Patent
Semiconductor device and method of manufacturing the same
TLDR
In this article, the authors proposed a semiconductor device consisting of a substrate, a device isolation insulating film, a plurality of transistors arranged in the transistor region, and an anti-inversion diffusion layer under the device-isolation insulation film.Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing rise in the threshold voltage in an HV transistor, and to provide a method for manufacturing the device. SOLUTION: The semiconductor device includes a semiconductor substrate 10, a device isolation insulating film 204 for isolating the semiconductor substrate 10 of a transistor region as a device region, a plurality of transistors arranged in the transistor region, and an anti-inversion diffusion layer 209 formed under the device-isolation insulation film 204. The transistor includes a gate insulating film 11 formed on the device region, a gate electrode 203 extending over the device isolation insulation film 204 formed on the gate insulation film 11, and a diffusion layer 18, formed on the surface of the semiconductor substrate 10 so as to sandwich the gate electrode 203 in between. The device-isolation insulating film 204 includes a region 204-1 juxtaposing the device region and a region 204-2 having the bottom deeper than that of the region 204-1. The anti-inversion diffusion layer 209 is formed under the region 204-2. COPYRIGHT: (C)2011,JPO&INPITread more
Citations
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References
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Patent
Asymmetrical non-volatile memory cell, arrays and methods for fabricating same
David K. Liu,Man Wong +1 more
TL;DR: In this paper, a nonvolatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily diffused diffused regions (16) formed in semiconductor layer (12), and a floating gate (24) insulatively overlies the channel area.
Patent
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TL;DR: In this article, a method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21 a ) in the cell array region, gate oxide film(21 b ) for a high-voltage circuit and gate oxide (21 c ) for lowvoltage circuits both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film ( 22 ).
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Metal oxide semiconductor field effect transistor
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