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Patent

SOI radio frequency switch with enhanced signal fidelity and electrical isolation

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TLDR
In this article, a doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom-semiconductor layer.
Abstract
A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.

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Citations
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Patent

System and Method for a Radio Frequency Switch

TL;DR: In this article, a circuit includes a plurality of switching networks coupled between a corresponding plurality of RF ports and a common RF port, and a control circuit, each of which includes a first switch coupled between its corresponding RF port and the common RF ports, such that the selectable network provides a DC path in a first state and a series capacitance in a second state.
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Wafer Backside Interconnect Structure Connected to TSVs

TL;DR: In this article, an integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrategies; and a metal feature on the back surface of the substrate.
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Bump Structure for Stacked Dies

TL;DR: In this article, a bump structure for stacked die configurations is provided, and an isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias.
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Multi-Layer Interconnect Structure for Stacked Dies

TL;DR: In this paper, a multi-layer interconnect structure for stacked die configurations is provided, where a backside of the semiconductor substrate is thinned to expose the through-substrate vias.
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Isolation Structure for Stacked Dies

TL;DR: An isolation structure for stacked dies is provided in this article, where a backside of the semiconductor substrate is thinned to expose the through-silicon via, and conductive element may be a solder ball or a conductive pad.
References
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Patent

Switch Circuit and Method of Switching Radio Frequency Signals

TL;DR: In this paper, a fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements, which includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.
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Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

TL;DR: In this article, a method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) was described, which can be adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFs, thereby yielding improvements in FET performance.
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TL;DR: In this paper, a decoupling capacitor is formed between the P + -type silicon layer and the N + − type silicon layer, which is connected to ground potential wiring GND and power supply potential wiring VDD.