Journal ArticleDOI
Suggestion for an i.c. fast parallel multiplier
Reads0
Chats0
TLDR
In this article, a general method for handling partial products in a parallel multiplier is proposed, which leads to a network of AND gates and full adders, availables as i.c.s which can have an operation time of less than 10 ns per bit.Abstract:
A general method for handling partial products in a parallel multiplier is proposed. It leads to a network of AND gates and full adders, availables as i.c.s which can have an operation time of less than 10 ns per bit of the result.read more
Citations
More filters
Journal ArticleDOI
Effective Pipelining of Digital Systems
TL;DR: In this paper, the authors present quantitative techniques for the evaluation and comparison of pipelined digital systems based on three measures of effectiveness: delay, average time/operation, and average cost/operation.
Journal ArticleDOI
Multiplexer-based array multipliers
TL;DR: In this article, the synchronous computation of the partial sums of the two operands is proposed for the parallel multiplication of two n-bit numbers, which permits an efficient realization of parallel multiplication using iterative arrays.
Journal ArticleDOI
Pipelining of Arithmetic Functions
TL;DR: Two addition and three multiplication algorithms were studied to see the effect of pipelining on system efficiency and a definition of efficiency was derived to compare the relative merits of various algorithms and implementations for addition and multiplication.
Journal ArticleDOI
FOCUS microcomputer number system
Albert D. Edgar,Samuel C. Lee +1 more
TL;DR: FOCUS has the wide-ranging character of floating-point numbers with a uniformity of state distributions that give FOCUS better than a twofold accuracy advantage over an equal word length floating- point system.
Journal ArticleDOI
Synthesis and Comparison of Two's Complement Parallel Multipliers
John A. Gibson,R.W. Gibbard +1 more
TL;DR: A machine word mathematical formulation is applied to analysis and synthesis of circuits for signed binary number multiplication with complemented multiplier/multiplicand or complemented partial product word corrections to offer advantages in circuit symmetry and algorithmic structure.
References
More filters
Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Journal ArticleDOI
Iterative logical network for parallel multiplication
TL;DR: In this article, a logical network is proposed, and an example of an iterative array formed using it is discussed, as well as an algorithm based on it for iterative arrays.