Patent
System and method for processor pipeline control by selective signal deassertion
TLDR
In this article, a processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts, where exceptional conditions are signaled within the processor by deasserting the LoadX signals required by that exception.Abstract:
A processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts. Each pipeline stage has associated with it a signal called "LoadX", where X is the pipeline stage name, e.g., LoadID. Instead of signalling exceptional conditions in terms of the event, e.g., "cache miss", exceptional conditions are signalled within the processor by deasserting the LoadX signals required by that exception. When the pipeline control for one pipestage is deasserted, in order to prevent previous instructions from entering the stalled pipestage, the detector of the exceptional condition must deassert all LoadX control signals for stages previous to X as well.read more
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Patent
Selective power-down for high performance CPU/system
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James S. Blomgren,Earl T. Cohen +1 more
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Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline
TL;DR: In this article, a microprocessor comprises a plurality of instruction pipelines, each of which is composed of a set of stages for processing a stream of instructions, and circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other instructions.
References
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Patent
Pipeline signal processor
TL;DR: In this article, a signal processor including a programmable arithmetic controller and a pipeline arithmetic unit controlled by such controller is described, where the arithmetic unit includes a plurality of serially coupled processing levels.
Patent
Data processing apparatus and method employing instruction pipelining
TL;DR: In this article, a data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline, each pipeline has a plurality of serially operating stages.
Patent
Data interface apparatus for multiple sequential processors
TL;DR: In this article, the authors present an approach for transferring data between multiple peripheral processors (PPs) which are operating under control of a host processor in a multi-processor computer system.
Patent
Pipe line high speed signal processor
David D. Lynch,Lee W. Tower +1 more
TL;DR: In this paper, a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing paths, each comprising stages through which data being processed is stepped, each stage corresponding to only one register of the control pipeline.