Journal ArticleDOI
Systolic array processing of the Viterbi algorithm
C.-Y. Chang,Kung Yao +1 more
TLDR
It is shown that as the length of the code becomes large, the systolic Viterbi decoder maintains a regular and general interconnection structure as well as moderate throughput rate gain over the sequential Viterba decoder.Abstract:
Results on efficient forms of decoding convolutional codes based on the Viterbi algorithm by using systolic arrays are presented. Various properties of convolutional codes are discussed. A technique called strongly connected trellis decoding is introduced to increase the efficient utilization of all the systolic array processors. Issues dealing with the composite branch metric generation, survivor updating, overall system architecture, throughput rate, and computational overhead ratio are also investigated. The scheme is applicable to both hard and soft decoding of any rate b/n convolutional code. It is shown that as the length of the code becomes large, the systolic Viterbi decoder maintains a regular and general interconnection structure as well as moderate throughput rate gain over the sequential Viterbi decoder. >read more
Citations
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Journal ArticleDOI
Low-power Viterbi decoder for CDMA mobile terminals
Inyup Kang,A.N. Willson +1 more
TL;DR: The Viterbi decoder presented here is the lowest power and smallest area core in its class, to the best of the authors' knowledge.
Journal ArticleDOI
High-performance VLSI architecture for the Viterbi algorithm
TL;DR: A regular and modular design appropriate for the VLSI implementation in which the only necessary communications between processors are the data recirculations between stages.
Journal ArticleDOI
FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder
TL;DR: An adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed and it is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive ViterBI algorithm, without degradation in the error performance.
Journal ArticleDOI
Using combinatorial optimization to design good unit-memory convolutional codes
A. Said,R. Palazzo +1 more
TL;DR: A method for designing good unit-memory convolutional codes is presented, based on the decomposition of the original problem into two easier subproblems that can be formulated as optimization problems and solved by efficient heuristic search algorithms.
Journal ArticleDOI
High-performance Viterbi decoder with circularly connected 2-D CNN unilateral cell array
TL;DR: A very-high-performance Viterbi decoder with a circularly connected two-dimensional analog cellular neural network (CNN) cell array is disclosed and its decoding speed becomes very high.
References
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TL;DR: The upper bound is obtained for a specific probabilistic nonsequential decoding algorithm which is shown to be asymptotically optimum for rates above R_{0} and whose performance bears certain similarities to that of sequential decoding algorithms.
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Why systolic architectures
TL;DR: The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.
Journal ArticleDOI
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TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
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TL;DR: A systolic system is a network of processors which rhythmically compute and pass data through the system, and almost all processors used in the networks are identical, so that a regular flow of data is kept up in the network.