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Journal ArticleDOI

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

TLDR
A mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay is developed.
Abstract
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.

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Citations
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Proceedings ArticleDOI

Novel physical unclonable function with process and environmental variations

TL;DR: Simulation results demonstrate that each IC can be uniquely characterized by PE-PUF with higher secrecy rate when compared to other PUFs that use only process variations.
Journal ArticleDOI

Power Droop Testing

TL;DR: A heuristic method to generate test sequences which create worst-case power drop by accumulating the high-frequency and low-frequency effects by employing a dynamically constrained version of the classical D-algorithm for test generation.
Proceedings ArticleDOI

Analyzing crosstalk in the presence of weak bridge defects

TL;DR: An extensive simulation study of various combinations of resistive bridges and crosstalk has been performed and several notable properties that have significant implications for test development have been discovered.
Journal ArticleDOI

Using a periodic square wave test signal to detect crosstalk faults

TL;DR: Built-in self test (BIST) scheme simplifies test generation and test application while obviating the fault occurrence timing issue and results show that coverage for the induced-glitch type of crosstalk fault for large benchmark circuits can easily exceed 90%.
Journal ArticleDOI

VLSI interconnects and their testing: prospects and challenges ahead

TL;DR: In this article, the functioning of very large-scale integration (VLSI) interconnects and modeling of interconnect and evaluate different approaches of testing interconnect's are explored.
References
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Book

Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI

An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits

TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Journal ArticleDOI

CMOS Circuit Speed and Buffer Optimization

TL;DR: An improved timing model for CMOS combinational logic is presented, which yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform.
Journal ArticleDOI

Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits

TL;DR: In this paper, a model for n parallel microstrip lines is developed for circuit simulation, which can accurately simulate the delay and crosstalk effects of interconnects in high-speed integrated circuits.
Proceedings ArticleDOI

Analytic models for crosstalk delay and pulse analysis under non-ideal inputs

TL;DR: A general methodology to analyze crosstalk to obtain insight into effects that are likely to cause errors in deep submicron high speed circuits and shows that crosStalk effects can be significantly aggravated by variations in the fabrication process.
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