Proceedings ArticleDOI
Minimizing power consumption in scan testing: pattern generation and DFT techniques
Kenneth M. Butler,Jayashree Saxena,Atul K. Jain,T. Fryars,J. Lewis,Graham G. Hetherington +5 more
- pp 355-364
TLDR
Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.Abstract:
It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.read more
Citations
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Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Journal ArticleDOI
Power Supply Noise in SoCs: Metrics, Management, and Measurement
TL;DR: Two metrics that quantify the impact of power supply noise are described and validates and are emerging as a replacement of SVD analysis for capturing theimpact of power Supply noise on the timing behavior of logic and memory cells.
Proceedings ArticleDOI
Power-aware test: Challenges and solutions
TL;DR: Concerns and challenges in power-aware test are highlighted, various practices drawn from both academia and industry are surveyed, and critical gaps that need to be addressed in the future are pointed out.
Proceedings ArticleDOI
On reducing peak current and power during test
TL;DR: Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.
Proceedings ArticleDOI
On generating pseudo-functional delay fault tests for scan designs
TL;DR: This work proposes new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states, which are essentially functional or pseudofunctional.
References
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Proceedings ArticleDOI
A case study of ir-drop in structured at-speed testing
TL;DR: This paper discusses the prac- tical issues associated with power consumption during at-speed tests, and delineates in more detail the nature of power-related phenomena encountered in structured speed tests.
Proceedings ArticleDOI
Static compaction techniques to control scan vector power dissipation
TL;DR: It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced.
Proceedings ArticleDOI
An analysis of power reduction techniques in scan testing
TL;DR: A scheme for reducing power is presented and analysis results on an industrial design are provided and it is shown that circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption.
Journal ArticleDOI
High-frequency, at-speed scan testing
Xijiiang Lin,Ron Press,Janusz Rajski,P. Reuter,T. Rinderknecht,B. Swanson,Nagesh Tamarapalli +6 more
TL;DR: New strategies where at-speed scan tests can be applied with internal PLL and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite are described.
Proceedings ArticleDOI
IDDQ and AC scan: the war against unmodelled defects
TL;DR: The effectiveness of the AC tests shows that targeting additional faults produces better quality than relying on peripheral coverage of existing tests, and all tests detect unique failures, indicating the presence of additional unmodelled faults.