Proceedings ArticleDOI
Test Propagation Through Modules and Circuits
B.T. Murray,John P. Hayes +1 more
- pp 748-757
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TLDR
In this article, the propagation characteristics of a module are represented by structures called ambiguity sets, which can be used for hierarchical test generation and design for testability, and also to aid in designing circuits suitable for high-level test generation.Abstract:
Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.read more
Citations
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Journal ArticleDOI
RTL Test Justification and Propagation Analysis for Modular Designs
Yiorgos Makris,Alex Orailoǧlu +1 more
TL;DR: An RTL analysis methodology is presented that identifies the test justification and propagation bottlenecks, facilitating a judicious DFT insertion process and two mechanisms for capturing, without reasoning on the complete functional space, data and control module behavior related to test translation are introduced.
Proceedings ArticleDOI
Testability and test protocol expansion in hierarchical macro testing
TL;DR: Test protocols play an important role within the macro tests strategy and describe, independently of the actual test pattern values and in detail how, at which terminals, and at which moments tests stimuli should be applied and responses should be observed.
Journal ArticleDOI
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test
TL;DR: By exploiting fine-grained design invariance, the proposed methodology enhances circuit reliability, and contributes a low-cost concurrent test direction, applicable to general RTL circuits.
Proceedings ArticleDOI
DFT guidance through RTL test justification and propagation analysis
Yiorgos Makris,Alex Orailoglu +1 more
TL;DR: In this article, the authors introduce a formal mechanism for capturing test justification and propagation related behavior of blocks, based on the identified test translation behavior, an RTL testability analysis methodology for hierarchical designs is derived.
References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI
A Knowledge-Based System for Designing Testable VLSI Chips
Magdy S. Abadir,Melvin A. Breuer +1 more
TL;DR: This article describes efforts to build a knowledge-based expert system for designing testable VLSI chips and introduces a framework for a methodology incorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques.
Journal ArticleDOI
Hierarchical test generation using precomputed tests for modules
B.T. Murray,John P. Hayes +1 more
TL;DR: A novel test generation technique for large circuits with high fault coverage requirements is described and preliminary results suggest that for circuits composed of datapath elements, speed improvements of three orders of magnitude over conventional techniques may be possible.
Proceedings ArticleDOI
ATPG for ultra-large structured designs
TL;DR: A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described, formed by optimally combining a fast fault simulator with a powerful test generator.
Journal ArticleDOI
Test generation for data-path logic: the F-path method
TL;DR: F-paths permit use of powerful, computer-aided test generation methods that have permitted routine targeting of 100% coverage of an expanded fault set, verification of success by simple postprocessing of RTL (resistor-transistor logic)-level good-logic simulation.