Proceedings ArticleDOI
Timing verification and optimization for the PowerPC processor family
R.E. Mains,T.A. Mosher,L.P.P.P. van Ginneken,R.F. Damiano +3 more
- pp 390-393
TLDR
The timing verification and optimization tools used for the 601, 603, 604 and 620 PowerPC processor designs are presented and a method for automatically deriving timing constraints for timing optimization is described.Abstract:
This paper presents the timing verification and optimization tools used for the 601, 603, 604 and 620 PowerPC processor designs. The timing verification is done by static timing analysis at the chip level, while the timing optimization is done by synthesis at the macro level. A method for automatically deriving timing constraints for timing optimization is described. >read more
Citations
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Journal ArticleDOI
Performance computation for precharacterized CMOS gates with RC loads
TL;DR: This paper presents a methodology for interfacing empirical gate models to reduced order RC interconnect models in terms of a nonlinear iteration procedure and generates a linear equivalent gate model which accurately captures the delays at the interconnect fan-out nodes.
Proceedings ArticleDOI
Coping with RC(L) interconnect design headaches
TL;DR: This tutorial paper will describe the technology trends which have brought about this interconnect dominance, then consider some of the modeling and analysis approximations available for both pre- and post-layout interconnect design.
Proceedings ArticleDOI
Timing metrics for physical design of deep submicron technologies
TL;DR: Some of the existing timing metrics that are suitable for use during physical design are overviewed, and new metrics and directions for future work are introduced.
Proceedings ArticleDOI
Static timing analysis for self resetting circuits
TL;DR: An approach that extends static timing analysis to a high-performance dynamic CMOS logic family called self-resetting CMOS (SRCMOS) and develops an SRCMos timing analyzer implemented as extensions to a standard static timingAnalysis program, thus facilitating its integration into an existing design system and methodology.
Static timing analysis forself resettingcircuits
TL;DR: In this paper, the authors describe an approach that extends static timing analysis to a high-performance dynamic CMOS logic family called self-fresetting CMOS (SRCMOS) and define various macrolevel timing tests which ensure that fundamental gate-level timing constraints are satisfied.
References
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Verifying clock schedules
Szymanski,Shenoy +1 more
TL;DR: In this paper, a simple polynomial time algorithm for clock schedule verification is presented, which was implemented and used to check the timing of all the circuits in the ISCAS-89 benchmark suite.
Proceedings ArticleDOI
Verifying clock schedules
TL;DR: A simple polynomial time algorithm for clock schedule verification is exhibited and was implemented and used to check the timing of all the circuits in the ISCAS-89 benchmark suite.
Proceedings ArticleDOI
The PowerPC 601 design methodology
T. Brodnax,M. Schiffli,F. Watson +2 more
TL;DR: To produce a marketable PowerPC microprocessor on a short development schedule, an appropriate balance was needed between a fully customized methodology and a standard cell approach.