Journal ArticleDOI
Using age registers for a simple load-store queue filtering
TLDR
This paper introduces two new LSQ filtering mechanisms with different design tradeoffs, but both explicitly rely on timing information as a primary instrument to rule out dependence violation and enforce memory dependences.About:
This article is published in Journal of Systems Architecture.The article was published on 2009-02-01. It has received 4 citations till now. The article focuses on the topics: Processor design.read more
Citations
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Journal ArticleDOI
Hybrid timing-address oriented load-store queue filtering for an x86 architecture
TL;DR: A straightforward filtering mechanism is introduced, which results in a more energy-efficient design than past techniques, using less and simpler hardware, and provides new opportunities for extra types of filtering, which lead to higher energy savings.
Computer Science & Technology Series
TL;DR: CACIC’11 was the seventeenth Congress in the CACIC series, with 11 Workshops covering a diversity of dimensions of Computer Science Research, and a total of 148 full papers, involving 393 authors and 77 Universities were accepted and 25 of them were selected for this book.
Reducing the LSQ and L1 data cache power consumption
Rubén Apolloni,P. Carazo,Fernando Castro,Daniel Chaver,Luis Piñuel,Francisco Tirado Fernández +5 more
TL;DR: Two techniques are proposed, one to filter accesses to the LSQ (Load-Store Queue) based on both timing and address information, and the other to filter Access to the first level data cache based on a forwarding predic- tor.
Reducing the LSQ and L1 Data Cache Power Consuption
Rubén Apolloni,Pablo Carazo Minguela,Fernando Castro,Daniel Chaver,Luis Piñuel,Francisco Tirado +5 more
TL;DR: In this paper, two techniques, one to load-Store queue accesses based on both timing and address information, and the other to first-level data cache accesses to the first level data cache based on a forwarding predictor, are proposed.
References
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Journal ArticleDOI
Space/time trade-offs in hash coding with allowable errors
TL;DR: Analysis of the paradigm problem demonstrates that allowing a small number of test messages to be falsely identified as members of the given set will permit a much smaller hash area to be used without increasing reject time.
Journal ArticleDOI
The SimpleScalar tool set, version 2.0
Doug Burger,Todd Austin +1 more
TL;DR: This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors.
Proceedings ArticleDOI
Wattch: a framework for architectural-level power analysis and optimizations
TL;DR: Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Proceedings ArticleDOI
Automatically characterizing large scale program behavior
TL;DR: This work quantifies the effectiveness of Basic Block Vectors in capturing program behavior across several different architectural metrics, explores the large scale behavior of several programs, and develops a set of algorithms based on clustering capable of analyzing this behavior.
Journal ArticleDOI
POWER4 system microarchitecture
TL;DR: The processor microarchitecture as well as the interconnection architecture employed to form systems up to a 32-way symmetric multiprocessor are described.