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Book ChapterDOI

VCC: A Practical System for Verifying Concurrent C

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TLDR
This paper motivates VCC, describes the verification methodology, the architecture of VCC is described, and the experience using VCC to verify the Microsoft Hyper-V hypervisor is reported on.
Abstract
VCC is an industrial-strength verification environment for low-level concurrent system code written in C. VCC takes a program (annotated with function contracts, state assertions, and type invariants) and attempts to prove the correctness of these annotations. It includes tools for monitoring proof attempts and constructing partial counterexample executions for failed proofs. This paper motivates VCC, describes our verification methodology, describes the architecture of VCC, and reports on our experience using VCC to verify the Microsoft Hyper-V hypervisor.

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Journal ArticleDOI

Featherweight VeriFast

TL;DR: VeriFast as mentioned in this paper is a prototype tool for the sound modular verification of safety and correctness properties of single-threaded and multithreaded C and Java programs, which has been used as a vehicle for exploration and validation of novel program verification techniques and for industrial case studies.
Proceedings ArticleDOI

VERONICA: Expressive and Precise Concurrent Information Flow Security

TL;DR: VERONICA is presented, the first program logic for proving concurrent programs information flow secure that supports compositional, high-precision reasoning about a wide range of security policies and program behaviours, and embodies a new approach for engineering such logics that can be re-used elsewhere, called decoupled functional correctness (DFC).

Formal Specification with JML

TL;DR: This introduction is written for all readers with an interest in formal specification of software in general, and anyone who wants to learn about the JML approach to specification in particular.
Proceedings ArticleDOI

Avoiding Hardware Aliasing: Verifying RISC Machine and Assembly Code for Encrypted Computing

TL;DR: This work checks RISC machine and assembly code to ensure that each memory address is calculated in exactly the same way at one write to and the next read from it, which allows programs to work correctly even in a hardware aliasing context.
Book ChapterDOI

Abstraction and subsumption in modular verification of C programs

TL;DR: Previous notions of Hoare-logic sub-specification are extended, to include framing and impredicative bifunctors and how this enables compositional modular verification of the functional correctness of C programs, in Coq, with foundational machine-checked proofs of soundness.
References
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Book ChapterDOI

Z3: an efficient SMT solver

TL;DR: Z3 is a new and efficient SMT Solver freely available from Microsoft Research that is used in various software verification and analysis applications.
Book ChapterDOI

A Temporal Logic of Nested Calls and Returns

TL;DR: This work introduces a temporal logic of calls and returns (CaRet) for specification and algorithmic verification of correctness requirements of structured programs and presents a tableau construction that reduces the model checking problem to the emptiness problem for a Buchi pushdown system.
Proceedings ArticleDOI

Separation logic: a logic for shared mutable data structures

TL;DR: An extension of Hoare logic that permits reasoning about low-level imperative programs that use shared mutable data structure is developed, including extensions that permit unrestricted address arithmetic, dynamically allocated arrays, and recursive procedures.
Book ChapterDOI

Amortised Memory Analysis Using the Depth of Data Structures

TL;DR: A related system for bounding the stack space requirements is described which uses the depth of data structures, by expressing potential in terms of maxima as well as sums, by adding extra structure to typing contexts to describe the form of the bounds.