Viability of pattern shift for defect-free EUV photomasks at the 7nm node

TLDR: In this paper, an empirical error budget to compensate for various measurement errors, based on the latest HVM inspection and write tool capabilities, is first established and then verified post-patterning.

Abstract: Several challenges hinder EUV photomask fabrication and its readiness for high volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. By using known defect locations on a blank, the mask design can be intentionally shifted to avoid patterning directly over a defect. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7 nm technology node. An empirical error budget to compensate for various measurement errors, based on the latest HVM inspection and write tool capabilities, is first established and then verified post-patterning. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed using OPC’d 7 nm node fully functional chip designs that were also recently used to fabricate working 7 nm node devices. Probability of defect-free masks are explored for various 7 nm mask levels, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks for the 7 nm node.