https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Block Contact Architectures for Nanoscale Channel Transistors

Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

CMOS devices with a single work function gate electrode and method of fabrication

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

With the planned introduction of double patterning techniques, the focus of attention has been on tool overlay performance and whether or not this meets the required overlay for double patterning. However, as we require tighter and tighter overlay performance, the impact of the selected integration strategy plays a key part in determining the achievable overlay performance. Very little attention has been given at this time to the impact of for example deposition steps, oxidation steps, CMP steps and the impact that they have on wafer deformation and therefore degraded overlay performance, which directly reduces the available overlay budget. Also, selecting the optimum alignment strategy to follow, either direct or indirect alignment, plays an important part in achieving optimum overlay performance. In this paper we investigate the process impact of various double patterning integration strategies and attempt to show the importance of selecting the right strategy with respect to achieving a manufacturable double patterning process. Furthermore, we report a methodology to minimize process overlay by modelling the non-linear grids for process induced wafer deformation and demonstrate best achievable overlay by feeding this information back to the relevant process steps.

Sources of overlay error in double patterning integration schemes

In this publication we introduce a new metric for process robustness of overlay metrology in microelectronic manufacturing. By straightforward statistical analysis of overlay metrology measurements on an array of adjacent, nominally identical overlay targets the Overlay Mark Fidelity (OMF) can be estimated. We present the results of such measurements and analysis on various marks, which were patterned using a DUV scanner. The same reticle set was used to pattern wafers on different process layers and process conditions. By appropriate statistical analysis, the breakdown of the total OMF into a reticle-induced OMF component and a process induced OMF component was facilitated. We compare the OMF of traditional box-in-box overlay marks with that of new gratingbased overlay marks and show that in all cases the grating marks are superior. The reticle related OMF showed an improvement of 30 % when using the new grating-based overlay mark. Furthermore, in a series of wafers run through an STI-process with different Chemical Mechanical Polish (CMP) times, the random component of the OMF of the new grating-based overlay mark was observed to be 40% lower and 50% less sensitive to process variation compared with Box in Box marks. These two observations are interpreted as improved process robustness of the grating mark over box in box, specifically in terms of reduced site by site variations and reduced wafer to wafer variations as process conditions change over time. Overlay Mark Fidelity, as defined in this publication, is a source of overlay metrology uncertainty, which is statistically independent of the standard error contributors, i.e. precision, TIS variability, and tool to tool matching. Current overlay metrology budgeting practices do not take this into consideration when calculating total measurement uncertainty (TMU). It is proposed that this be reconsidered, given the tightness of overlay and overlay metrology budgets at the 70 nm design rule node and below.

Characterization of overlay mark fidelity

With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent (~1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.

Wafer-shape based in-plane distortion predictions using superfast 4G metrology

EUV lithography is a candidate for device manufacturing for the 16nm node and beyond. To prepare for insertion into
manufacturing, the challenges of this new technology need to be addressed. Therefore, the ASML NXE:3100 preproduction
tool was installed at imec replacing the ASML EUV Alpha Demo Tool (ADT). Since the technology has
moved to a pre-production phase, EUV technology has to mature and it needs to meet the strong requirements of sub
16nm devices. We discuss the CD uniformity and overlay performance of the NXE:3100. We focus on EUV specific
contributions to CD and overlay control, that were identified in earlier work on the ADT. The contributions to overlay
originate from the use of vacuum technology and reflective optics inside the scanner, which are needed for EUV light
transmission and throughput. Because the optical column is in vacuum, both wafer and reticle are held by electrostatic
chucks instead of vacuum chucks and this can affect overlay. Because the reticle is reflective, any reticle (clamp)
unflatness directly translates into a distortion error on wafer (non-telecentricity). For overlay, the wafer clamping
performance is not only determined by the exposure chuck, but also by the wafer type that is used. We will show wafer
clamping repeatability with different wafer types and discuss the thermal stability of the wafer during exposure.

David Laidler

Papers

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

Sources of overlay error in double patterning integration schemes

Characterization of overlay mark fidelity

Wafer-shape based in-plane distortion predictions using superfast 4G metrology

Progress in EUV lithography towards manufacturing from an exposure tool perspective