Patent
Wide adder with critical path of three gates
TLDR
In this article, a pipelined circuit with a plurality of logic gates is described, the critical path through the plurality of gates being three gates delays for some embodiments, and the third level of logic comprising: a plurality-of-domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.Abstract:
Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signalsread more
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Patent
Implementing conditional statements in self-timed logic circuits
Steven P. Young,Brian C. Gaide +1 more
TL;DR: In this article, a pipelined routing path is used to route the self-timed select signal from the input circuit to the output circuit, where the output is coupled to receive the selftimed output from both the first and second logic circuits.
Patent
Circuits for sharing self-timed logic
Steven P. Young,Brian C. Gaide +1 more
TL;DR: In this paper, a pipelined routing path is used to route the self-timed enable signal from the input circuit to the output circuit, where the output is coupled to receive the first and second selftimed outputs from the shared logic circuit and to provide a selected one of the first or second outputs.
Patent
Compute-centric architecture for integrated circuits
Steven P. Young,Brian C. Gaide +1 more
TL;DR: In this article, an integrated circuit may include an array of interconnected substantially similar logic blocks, each including a multiplier circuit and a lookup table circuit, and the multiplier circuits in adjacent logic blocks may be coupled together via a multi-bit partial product bus.
Patent
Signed multiplier circuit utilizing a uniform array of logic blocks
Steven P. Young,Brian C. Gaide +1 more
TL;DR: A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks, each of which includes rows and columns of sub-circuits, e.g., logical AND gates and full adders as mentioned in this paper.
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Cascading input structure for logic blocks in integrated circuits
TL;DR: In this article, a cascading input structure for logic blocks in an integrated circuit is presented, which includes a plurality of substantially similar logic blocks arrayed to form a column of the logic blocks and a self-timed vertical cascade chain.
References
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Patent
Digital adder and method for adding 64-bit, 16-bit and 8-bit words
TL;DR: In this article, two levels of Kogge-Stone trees are used to generate group carries and propagate signals and the second level is used for generating the carry signals for the 64-bit case.
Proceedings ArticleDOI
Clock-delayed domino for adder and combinational logic design
Gin Yee,Carl Sechen +1 more
TL;DR: An innovative dynamic logic family, clock-delayed (CD) domino, was developed to provide gates with either inverting or non-inverting outputs, and the high speed and layout compactness of dynamic logic.
Patent
Clock-delayed pseudo-NMOS domino logic
TL;DR: In this article, a pre-charge transistor is used to couple the output node to the second power supply node during a precharge phase in the logic gate in a logic circuit.
Patent
Carry look-ahead adder
TL;DR: In this paper, a carry look-ahead system is proposed to speed up carry propagation in an adder using a carry-lookahead system, which is hierarchically used for plural adders.
Patent
Carry signal generating circuit
TL;DR: In this paper, the authors propose to make an adder fast by shortening the total carry signal generation time including precedent and trailing stages as to a precedent stage circuit and a trailing stage circuit which constitute the carry signal generating circuit by precedently processing part of logical operation of the trailing-stage circuit by the precedent stage.