Patent
Write assist circuit, memory device and method
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TLDR
In this article, a write assist circuit includes a first switch, a second switch and a bias voltage circuit, which generates an adjustable bias voltage lower than the power supply voltage at an output thereof.Abstract:
A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state.read more
Citations
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References
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Proceedings ArticleDOI
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry
Eric Karl,Yih Wang,Yong-Gee Ng,Zheng Guo,Fatih Hamzaoglu,Uddalak Bhattacharya,Kevin Zhang,Kaizad Mistry,Mark T. Bohr +8 more
TL;DR: A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon to address process variation and fin quantization at 22nm.
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Semiconductor memory device
TL;DR: In this paper, a data protection mechanism was proposed to protect already programmed data from being destroyed due to programming error at the time of programming the data, which can protect previously programmed data.
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Memory with reduced power supply voltage for a write operation
TL;DR: In this paper, a memory includes a selection circuit and a write assist circuit, which is coupled to the first input of the selection circuit for reducing a voltage at the power supply terminal of each of the plurality of memory cells during a write operation and in response to an asserted write assist enable signal.
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Non-volatile semiconductor memory device
TL;DR: In this paper, a non-volatile semiconductor memory device with a writing power source voltage exceeding a withstand voltage of a field effect transistor is presented. But the number of kinds of field effect transistors constituting the nonvolatile memory device is not reduced.