Proceedings ArticleDOI
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry
Eric Karl,Yih Wang,Yong-Gee Ng,Zheng Guo,Fatih Hamzaoglu,Uddalak Bhattacharya,Kevin Zhang,Kaizad Mistry,Mark T. Bohr +8 more
- pp 230-232
TLDR
A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon to address process variation and fin quantization at 22nm.Abstract:
Future product applications demand increasing performance with reduced power consumption, which motivates the pursuit of high-performance at reduced operating voltages. Random and systematic device variations pose significant challenges to SRAM V MIN and low-voltage performance as technology scaling follows Moore's law to the 22nm node. A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon. Tri-gate technology reduces short-channel effects (SCE) and improves subthreshold slope to provide 37% improved device performance at 0.7V. Continuous device width sizing in planar technology is replaced by combining parallel silicon fins to multiply drive current. Process-circuit co-optimization of transient voltage collapse write assist (TVC-WA) and wordline underdrive read assist (WLUD-RA) features address process variation and fin quantization at 22nm and enable a 175mV reduction in the supply voltage required for 2GHz SRAM operation. Figure 13.1.1 shows an SEM top-down view of a 0.092μm2 high-density 6T SRAM bitcell (HDC) and a 0.108μm2 low-voltage 6T SRAM cell (LVC) after gate and diffusion processing. Computational OPC/RET techniques extend the capabilities of 193nm immersion lithography to allow a 1.85× increase in array density relative to 32nm designs [1].read more
Citations
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Journal ArticleDOI
The era of hyper-scaling in electronics
TL;DR: This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques.
Proceedings ArticleDOI
Memristor based computation-in-memory architecture for data-intensive applications
Said Hamdioui,Lei Xie,Hoang Anh Du Nguyen,Mottaqiallah Taouil,Koen Bertels,Henk Corporaal,Hailong Jiao,Francky Catthoor,Dirk Wouters,Linn Eike,Jan van Lunteren +10 more
TL;DR: The paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability.
Proceedings ArticleDOI
22-nm fully-depleted tri-gate CMOS transistors
TL;DR: At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process resulting in the highest drive currents yet reported for NMOS and PMOS.
Journal ArticleDOI
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V MIN applications
Jonathan Chang,Yen-Huei Chen,Wei Min Chan,Singh Sahil Preet,Hank Cheng,Fujiwara Hidehiro,Jih-Yu Lin,Kao-Cheng Lin,John Hung,Robin Lee,Hung-jen Liao,Jhon-Jhy Liaw,Quincy Li,Lin Chih-Yung,M.C. Chiang,Shien-Yang Wu +15 more
TL;DR: Two write-assist techniques are proposed: 1) suppressed coupling signal negative bit-line (SCS-NBL) technique and 2) write recovery enhanced lower cell-VDD (WRE-LCV) technique to reduce the SRAM minimal supply voltage.
Journal ArticleDOI
An Overview of Nonvolatile Emerging Memories— Spintronics for Working Memories
TL;DR: Current status of spintronics developments including not only STT-MRAM but also nonvolatile logic LSI is described, which are particularly suitable for working memory applications.
References
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Harold Pilo,Igor Arsovski,Kevin A. Batson,Geordie Braceras,John A. Gabric,Robert M. Houle,Steve Lamphier,Frank Pavlik,Adnan Seferagic,Liang-Yu Chen,Shang-Bin Ko,Carl J. Radens +11 more
TL;DR: A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology with improved stability and performance and a bit-cell-tracking delay circuit improves both performance and yield across the process space.
Journal ArticleDOI
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation
Hyunwoo Nho,Pramod Kolar,Fatih Hamzaoglu,Yih Wang,Eric Karl,Yong-Gee Ng,Uddalak Bhattacharya,Kevin Zhang +7 more
TL;DR: An adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die is introduced.
Proceedings ArticleDOI
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management
Yih Wang,Uddalak Bhattacharya,Fatih Hamzaoglu,Pramod Kolar,Yong-Gee Ng,Liqiong Wei,Yuegang Zhang,Kevin Zhang,M. Bohr +8 more
TL;DR: In this paper, the authors developed a high-performance voltage-scalable SRAM design in 32nm logic CMOS featuring 2nd-generation high-κ metal-gate transistors and 4th-generation strained silicon, achieving 2× improvement in density and 15% faster access speed when compared to the 45nm design at the same voltage.