Showing papers on "Adder published in 1985"

Adder/substractor for variable length numbers

Abstract: An adder/subtractor wherein N/2 two bit adders are connected to allow the addition of numbers having N bits, each one of the two bit adders having associated control circuitry adapted: (a) to cause each two bit adder either to add applied bits directly or to add one applied bit and the "two's complement" of the other bit; and (b) to electrically separate any selected ones of the two bit adders from the others.

Depletion/enhancement CMOS for a lower power family of three-valued logic circuits

Abstract: A new family of ternary logic circuits that uses both depletion and enhancement types of complementary metal-oxide semiconductor (CMOS) transistors is presented. These circuits use two power supplies, each below the transistor's threshold voltages, and do not include resistors. Circuit designs of basic ternary operators (inverters, NAND, NOR) are described. These basic ternary operators can be used as building blocks in the VLSI implementation of three-valued digital systems. An example of the design of a ternary full adder using this family of logic circuits is also presented.

High performance signal processor

Abstract: A monolithic high performance processor for computing digital signal processing algorithms based on the Fast Fourier Transform. The monolithic processor employs an array of bit-serial multipliers which cooperate with bit-serial adder/substractors to produce fast results with great precision, with reduced printed-circuit board space, and with low power requirements. The processor uses local asynchronous control and simple interfacing with the host computer. The processor, which is applicable to a broad spectrum of digital signal processing, including digital audio, radar/sonar, seismic and speech processing, operates in a variety of modes which allow the device to perform Fast Fourier Transforms, Inverse Fast Fourier Transforms, windowing, multiplication, Finite Impulse Response filtering, convolution and correlation.

AN XxY BIT ARRAY MULTIPLIER/ACCUMULATOR CIRCUIT

Abstract: An XxY bit array multiplier/accumulator circuit (10), where X and Y are integers, for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders (13) and multiplexers (12) in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry (14) and signed/unsigned modes of operation (15) are provided.

Some optimal schemes for ALU implementation in VLSI technology

Abstract: An efficient scheme for carry propagation in an ALU implemented in n-MOS technology is presented. An algorithm that determines the optimum division of the carry chain of a parallel adder for various data path sizes is developed. This yields an implementation of a fast ALU which due to its regular structure occupies a modest amount of silicon. The speed of the implementation described is comparable to the carry look-ahead scheme. Our method is based on the optimization of the carry path implemented in n-MOS technology but the results can be applied to other technologies.

A Fast Serial-Parallel Binary Multiplier

Abstract: A fast serial-parallel (FSP) multiplier design is derived from the carry-save add-shift (CSAS) multiplier structure. The CSAS technique accepts multiplier bits serially (lsb first) and produces outputs serially (lsb first). Multiplication of two n bit unsigned numbers requires 2n clock cycles to complete the process out of which n clocks are used for n-row carry-save additions, and the other n clocks are utilized only to propagate the remaining carries. This CSAS structure is modified so that it operates as a CSAS unit for the first n clocks and reconfigures itself as an n bit ripple-carry parallel adder at the (n + 1)st clock, thus allowing the carries to ripple through, eliminating the delay due to storage elements during the last n clocks. It is shown that this modification results in an about one-third increase in speed for an approximately one-third increase in hardware. The technique is extended to signed numbers represented in 2's complement form. Also, it is shown how these implementations can be modularized.

Digital frequency modulator

Abstract: An MSK modulator includes a source of digital sawtooth signals having a recurrence rate equal to the desired recurrence rate of the unmodulated carrier. The digital sawtooth signal is applied to an adder together with a phase control digital signal. The phase control digital signal phase-shifts the digital sawtooth signal. The phase-shifted digital sawtooth signal is applied to a sine ROM to produce a digital sinusoid with an unmodulated recurrence rate equal to the recurrent rate of the digital sawtooth signal. When the phase control signal is an accumulated signal, the digital sinusoid is frequency-modulated. The phase control signal for MSK modulation is a ramp signal generated by a controlled accumulator. The accumulator includes a controllable clocked adder/subtractor, the output of which is coupled by way of a register back to an input. The other input of the adder/subtractor is coupled to receive a fixed ramp rate controlling word. At each clock cycle, the accumulator adds (subtracts) the ramp rate word from the sum under the control of the MARK (SPACE) information content of the information signal to form a two-frequency MSK modulation. More general frequency modulation is accomplished by an accumulator with an input word which responds to the instantaneous amplitude of the information signal. A clocked delay and a subtractor indicate the direction of frequency deviation.

An integration of all refractory Josephson logic LSI circuit

Abstract: An integration process for the fabrication of an all refractory Josephson LSI logic circuit is described. In this process, niobium nitride and niobium double-layered Josephson junctions were integrated using a reactive ion etching with a 2.5 μm minimum feature. A highly selective and anisotropic RIE process and a planarizing technology have been developed for intagrating a circuit with LSI complexity. For evaluating the process capability, test vehicle circuits with MSI/LSI level complexity have been designed and fabricated using this process. An 8 bit ripple carry adder and a 4×4 bit parallel multiplier have been integrated with Josephson four junction logic ( 4JL ) gates, the largest of which contains more than 2800 Josephson junctions. Both functionality and high-speed performance testings have been successfully performed with these test circuits.

Regular, area-time efficient carry-lookahead adders

Abstract: For fast binary addition, a carry-lookahead (CLA) design is the obvious choice [OnAt83, BaJM831. However, the direct implementation of a CLA adder in VLSI faces some undesirable limitations. Either the design lacks regularity, thus increasing the design and implementation costs, or the interconnection wires are too long, thus causing area-time inefficiency and limits on the size of addition. Brent and Kung solved the regularity problem by reformulating the carry chain computation [BrKu82]. They showed that an n-bit addition can be performed in time O(log n), using area O(n log n) with maximum interconnection wire length o(n). In this paper, we give an alternative log n stage design which is nearly optimum with respect to regularity, area-time efficiency, and maximum interconnection wire length.

Driving circuit for brushless DC motors

Abstract: A driving circuit for a brushless DC motor having a small amount of torque ripple comprises a magnetic pole position detecting circuit (110) for detecting positions of magnetic poles of a rotor magnet (9) for delivering polyphase signals indicating the positions, a rectifier adder circuit (40) for producing a sum of positive or negative portions of the polyphase signals from the magnetic pole position detecting circuit (110), a first error amplifier (50) for adjusting a gain of the magnetic pole position detecting circuit (110) to make an output signal of the rectifier adder circuit (40) to be proportional to an instruction signal, a power supply circuit (101, 102, 103) for supplying currents to armature coils (4, 5, 6) in response to the polyphase signals, a modulating signal producing circuit (120) for producing a modulating signal synchronised with the rotation of the motor, and a second error amplifier (70) for adjusting a gain of the power supply circuit (101, 102, 103) to make the currents supplied to the armature coils (4, 5, 6) to be proportional to the modulating signal.

Closed loop control circuitry for step motors

Abstract: Control circuitry for a self-synchronously driven step motor under closed loop control includes, for determining the rotor position, a technologically simplified back EMF waveform detector circuit which includes fewer than five operational amplifiers, and preferably only one operational amplifier, and which delivers, for each motor phase, a back EMF signal and the negative thereof. Use can be made of these signals individually or in various combinations, with the aid of a back EMF selector arrangement and an adder connected thereto, for controlling the stator field. By sum and difference formation of back EMF signals by the adder and by assigning such signals each to a respective energization state of the motor phases, the rotor can be moved by half-steps as well as full-steps, to provide a finer degree of control. Additionally it is possible with such circuitry to detect the end position of the rotor and its maximum degree of overrunning, which yield values that can be used for achieving desired damping of the rotor.

Integrated-Circuit Logarithmic Arithmetic Units

Abstract: This correspondence examines integrated-circuit logarithmic arithmetic units which include adders, subtracters, multipliers, and dividers. The design of these arithmetic units is reviewed, and an example arithmetic unit which performs multiplication followed by addition is designed in detail. The design results are used to develop a size and speed comparison of integrated-circuit logarithmic and fixed-point arithmetic units. This comparison is exercised through a video signal processing example. It is concluded from this comparison that logarithmic arithmetic units are smaller than, and as fast as, fixed-point arithmetic units with comparable capabilities in digital signal processing applications characterized by large dynamic range and moderate computational accuracy requirements. Further, this comparison quantitatively illustrates the interaction of digital-signal-processing and integrated-circuit issues in the design of special-purpose digital signal processors.

High-speed multiplier having carry-save adder circuit

Abstract: A high-speed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation. That is, a carry signal of a full adder of two stages over is input with a speed increase of 1/2T FA .

Digital repeater with 3-way branching of service channels

Abstract: A novel 3-way digital branching network located at a telecommunications repeater branches digital service channel signals into and out of the digital transmission system. On the drop side a first adder combines the West-to-East and East-to-West digital service channel signals before being converted to analog signals for use by the local service channel equipment. On the insert side the locally generated service channel signals are digitized and then digitally combined with the through path signals by a second and third adder for insertion into the West-to-East and East-to-West digital transmission paths.

Conditional carry techniques for digital processors

Abstract: A relatively small set of cells is shown for constructing a conditional carry adder for two N-digit operands. The structure and organization of the cells is adaptable for constructing any length adder with both high absolute performance and low circuit complexity in LSI by either bipolar or MOS techniques. In addition, the technique is shown adapted for use as either an incrementor or as a priority encoder.

Method of, and apparatus for, transforming a digital data sequence into an encoded form

Abstract: A converter or running-key for generator producing pseudo-random sequences under the supervision of a secret or confidential key or code is substantially formed by a combination device containing a memory circuit and a feedback circuit. Periodic digital sequences are summed in an adder circuit, and the thus obtained composite digital sequence is separated in a divider circuit. A part of this composite digital sequence is used as a digital feedback sequence which is fed to an input of the same adder circuit through the feedback circuit comprising an auxiliary digital memory device or storage and an auxiliary logic circuit. In this manner, the desired memory and feedback is achieved which results in more complicated or complex pseudo-random sequences. In an advantageous exemplary embodiment, a substitution block is inserted as the auxiliary digital memory device or storage. This substitution block can be implemented by a commercially available read-and-write memory (RAM).

Microphone apparatus having a variable directivity pattern

Abstract: A microphone apparatus includes an array of equally spaced microphones divided into a center subarray and a pair of side subarrays located one on each side of the center subarray. A first weighting network having a plurality of weighting factors impresses a first weighting function on signals from the center subarray. Second and third weighting networks each having a plurality of weighting factors impress second and third weighting functions respectively on signals from the side subarrays. The first, second and third weighting functions correspond respectively to center and side portions of a total function. Signals from the first weighting network are summed in a first adder, signals from the second and third weighting networks being summed in a second adder and cmbined with the output of the first adder in a third adder to produce an output signal. A variable directivity pattern is obtained by a level setting means which allows adjustment of the level of the output signal from the second adder in a predetermined relationship with the level of the output signal from the first adder.

Picture transmission system using secondary differential variable sampling rate coding

Abstract: A picture transmission system of the present invention is adapted to code picture data by a variable sampling rate coding system to transmit the same. Picture data are stored in a frame memory (16) of a transmission area so that differential values between the same and predictors from a predictive circuit (43) are obtained by a subtracter (41) and compression-coded by a variable sampling rate compression circuit (42) to be transmitted. The compression-coded differential values are expansion-decoded by a variable sampling rate expansion circuit (40) so that original differential values are supplied to an adder (45). The adder (45) adds up the differential values with predictors, to produce predictors for subsequent sampling points. In a receiving area, transmitted codes are expansion-decoded by a variable sampling rate expansion circuit (51), so that the decoded values are added up with predictors from a predictive circuit (53) by an adder (52) to output the original picture data. Preposition prediction and variable sampling rate decoding are thus combined to enable, in the receiving area, automatic correction of compression/expansion errors caused in the transmission area.

Systolic complex multiplier

Abstract: A complex multiplier includes a carry-sum systolic array (26) of multiplier cells for processing a multiplicand therethrough in accordance with a modified Booths algorithm. The multiplier performs two multiplications and two addition/substraction operations. A ROM (12) provides the multipliers for the operation which are input to a booth decoder (50) through a delay line (48). The delay line (48) delays pairs of bits by one bit each to synchronize with the flow of the partial products through the array (26). After one product is processed in the array (26), the sum and carry is fed back to the input through a delay (52). This delay allows for processing two products in a single operation with a subsequent operation interleaved therebetween. When one operation is complete, it is output to adders (64) and (66) to perform a complex addition and substraction with another input data vector. This addition occurs at one half the rate of the pipeline (26) due to the interleaving of the two operations.

Implementing FIR filters with distributed arithmetic

Abstract: A new approach for implementing FIR filters with distributed arithmetic is presented. This approach uses a RAM to store the input sequences, utilizes a partitioned ROM to store the combinational values of the filter coefficients, and provides the arrangement techniques for adders which are used for accumulating the partial product and the sum. The proposed approach results in a very low storage requirement and enables a cost-effective implementation of fast high-order FIR filters.

Floating point arithmetic unit

Abstract: A data processing system includes multiple floating point arithmetic units, for example, an adder and a multiplier Two putaway busses and two bypass busses are connected to a register file and waiting stages, associated with the arithmetic units, respectively A special source register is included for keeping track of the source of any result on the busses so that the registers may be connected to the appropriate bus on which the result is to appear in accordance with a busy or mark bit set in each register in the file and in the waiting stage This allows multiple data items to exit the pipes during any cycle Therefore, two or more results are produced each cycle

Digital adder-subtracter with tentative result correction circuit

Abstract: For reduction in circuit complexity, there is disclosed a high speed digital arithmetic unit comprises a plurality of binary adders in cascade arrangement, each binary adder comprising carry lookahead means for generating a carry signal representative of an actual carry bit based on a segment of a first binary number, a corresponding segment of a second binary number and a carry signal fed from an adder located at a lower position, adding means for adding the segment of the first binary number to the corresponding segment of the second binary number in parallel operation with the carry lookahead means, the adding means simultaneously adding a suspense carry to a partial sum of the segments for generation of a temporary result, and final result determination means operative to generate a final result based on the partial sum in accordance with the actual carry fed from the lower adder.

Design of a fast inner product processor

Abstract: This paper presents the design of a fast inner product processor, with appreciably reduced latency and cost The inner product processor is implemented with a tree of carry propagate or carry save adders; this tree is obtained with the incorporation of three innovations in the conventional multiply/add tree: (1) The leaf-multipliers are expanded into adder subtress, thus achieving an O(logNb) latency, where N denotes the number of elements in a vector and b the number of bits in each element (2) The partial products, to be summed in producing an inner product, are reordered according to their "minimum alignments", bringing approximately a 20% saving in hardware (3) The reordering also truncates the carry propagation chain in the final propagation stage by 2 log b − 1 positions, significantly reducing the latency further A form of the Baugh and Wooley algorithm is adopted to implement two's complement notation with changes only in peripheral hardware

Data error detection and correction circuit

Abstract: PURPOSE:To attain detection and correction of a data error by means of a read Solomon code in a short time by providing a connecting means connecting function blocks and controlling the control means based on a timing signal. CONSTITUTION:A syndrome operating section 21 calculates syndrome by accumulating sequentially each data applied via a data bus DABS2 and outputs the result to an internal bus INBS. A multiplication/division section 22 applies multiplication/division of the syndrome of a data outputted to the INBS. An adder/ subtractor section 23 applies addition/subtraction to the result of the multiplication/division section 22. Then a double error detection section 24 detects whether or not a double error exits based on an output of the adder/subtractor section 23. Moreover, a single circuit detection section 25 detects the data of the INBS as to whether or not a single error exists. A data correction section 26 corrects erroneous data based on the data applied via each INBS for the data applied via a DABS2. The operation of each functional block is controlled by a timing signal of a timing signal generating circuit 27.

Analog-digital converter

Abstract: PURPOSE:To prevent the deviation of a comparison reference level from being increased due to a change of the lapse of time by applying control that a number being a lower limit of an output of an AD converter of a ramp reference signal inserted during the ineffective period of a signal to be converted is minimized CONSTITUTION:The ramp reference signal (b) is fed to an adder 4 during the ineffective period of a signal (a) to be converted to obtain a signal C Then a signal whose level is shifted downward from the output of the adder 4 by the AD converter 1 and a DC level control circuit 3 is led to the AD converter 2, where number existing at lower limit is counted by a counter circuit 5 Then the setting number is compared (6) with number of the content of the counter circuit 5, the result is subject to DA conversion 7, and when the number of the content of the counter circuit 5 is larger than the setting number, the downward level shift in the DC level control circuit 3 is decreased When smaller, the downward level shift is increased to activate a negative feedback loop, resulting that the output of the counter circuit 5 and the setting number are made identical

Self-synchronizing scrambler

Abstract: A self-synchronizing scrambler for high bit rates has a number of scrambler stages supplied in parallel with bits of a signal to be scrambled, each scrambler stage having a series-connected pair of modulo-2 adders, and at least one shift register. A selected number of scrambler stages in the scrambler may include an additional shift register depending upon the number p of parallel bits in the signal to be scrambled, and the total number n of shift registers in the scrambler. The number of scrambler stages having two shift registers is n-p and the number of following scrambler stages having one shift register is 2 p-n. For suppressing short periods, a further modulo-2 adder can be connected between the original two modulo-2 adders, the additional modulo-2 adder inverting at least one bit of the signal for the short periods.

Vibration-proof optical device

Abstract: PURPOSE: To compensate blur of an image very accurately by driving a correcting optical system for each acceleration component. CONSTITUTION: An arithmetic circuit 10 for moving acceleration of the image due to the shift of a photographic optical axis calculates a transverse magnifica tion β in accordance with the output signal of a focus position signal detecting part 5b and multiplies this magnification by the output of an acceleration sensor S1 and outputs the multiplication result. An arithmetic circuit 20 for moving acceleration of the image due to rotation of the optical axis around a principal point weights the difference between the output of an acceleration sensor S2 outputted from a divider circuit 30 and the output of the acceleration sensor S1 as preliminarily determined by a focus position signal and outputs the weighted result. Both these signals are added by an adder circuit 40 to obtain the moving speed of the image. the acceleration signal of the image is fed forward to a driving circuit 60, and the circuit 60 performs the forecasting control and drives an actuator while referring to a characteristic input circuit 70 of the actuator. COPYRIGHT: (C)1987,JPO&Japio

Frequency demodulation circuit with zero-crossing counter

Abstract: A digital frequency demodulator circuit works on the principle of determining the number of zero crossings of a band-limited input signal in a given period of time, in corresponding prior art analog circuits. The circuit includes an analog-to-digital converter, three delay elements, two edge detectors, an up/down counter, two arcsin read-only memories, a 1/2 multiplier and a multiple adder.

Digital television signal processing circuit

Abstract: An analog video signal of a PAL system is converted into a digital video signal by an A/D converter. The digital video signal is supplied to a delay device so as to be subjected to hue correction and Y/C separation. The delay device generates a plurality of digital video signals with different delay times. The digital video signals S1(t) and S2(t) obtained from the delay device are supplied to a first subtracter, and the digital video signals S3(t) and S4(t) are supplied to a second subtracter. The outputs from the first and second subtracters are supplied to a third subtracter, and the output from the third subtracter is multiplied with a coefficient, thereby obtaining a first chrominance signal U(t). The outputs from the first and second subtracters are supplied to a first adder, and the output from the first adder is multiplied with a coefficient, thereby obtaining a second chrominance signal V(t).