Showing papers on "AND gate published in 1974"

MINI: a heuristic approach for logic minimization

Abstract: MINI is a heuristic logic minimization technique for many-variable problems. It accepts as input a Boolean logic specification expressed as an input-output table, thus avoiding a long list of minterms. It seeks a minimal implicant solution, without generating all prime implicants, which can be converted to prime implicants if desired. New and effective subprocesses, such as expanding, reshaping, and removing redundancy from cubes, are iterated until there is no further reduction in the solution. The process is general in that it can minimize both conventional logic and logic functions of multi-valued variables.

Electronic security card and system for authenticating card ownership

Abstract: An electronic security card and system for authenticating ownership of the card is disclosed. The system comprises a security card and a terminal. The security card includes logic circuitry which is responsive to a plurality of input signals and which is operative to provide an output signal if the input signals are in a preselected sequence and to develop a feedback control signal which is applied to, and deactivates, the logic circuitry if the input signals are not in the preselected sequence. The terminal comprises a source of input signals, a switching network for selectively interconnecting the source to the logic circuitry so as to apply a sequence of input signals to the logic circuitry when the security card is received by the terminal, and an indicator responsive to the output signal and operative to provide an indication of the authenticity of the user of the security card. The logic circuitry includes a plurality of stages, each of which comprises an AND gate and a flip-flop, and which is arranged so that the signal developed at the output of one of the stages is applied to gate a preceding stage.

Characteristics and applications of a Schottky-barrier-gate Gunn-effect digital-device

Abstract: The theory is developed for the characteristics of a Schottky-barrier-gate Gunn-effect digital-device (SBG GEDD). The four basic parameters, i.e., relative field drop, minimum trigger-field, minimum trigger-pulse duration, and trigger capability, are defined and evaluated numerically for GaAs. Then the device characteristics such as output current, maximum trigger sensitivity, trigger capability, amplification factor, fan-out, noise margin, jitter, unidirectionality, and power-delay product, are derived and calculated for SBG GEDD's with different doping densities and different sizes by using the results of preliminary measurements. The features of SBG GEDD are 1) great trigger capability, 2) good trigger sensitivity, 3) high unidirectionality, 4) small input capacitance, 5) high response-speed and short delay time, 6) small power-delay product, 7) large fan-out, and 8) simple device and circuit constructions. Some applications are demonstrated to high-speed pulse repeaters and logic circuits.

Time split array logic element and method of operation

Abstract: A standard logic array can be electrically altered at different time intervals to execute complex logic functions. Input variables to the array are processed in a network to generate sets of implicants of a complex function in one or more time periods. The implicants constituting the function are processed through a logic network or matrix as the logic personality of the matrix is altered. The implicant and logic networks may be personalized by (a) structure, (b) time signals, (c) personality signals, and (d) any combination of (a), (b) and (c). The standard array executes complex functions in a single time period or by processing one or more implicants in groups at different time periods. The testability of the array may be improved by appropriate interconnections of the array elements. The invention reduces the number of logic elements or part numbers a system designer must assemble to achieve desired objectives for a data processing machine. The arrays can be produced, stockpiled and structurally personalized at a later time as required by a system designer. The method of operating the array is compatible with data processing machine programming and operation.

Process for the production of a pair of complementary field effect transistors

Abstract: A process for the production of a pair of complementary field effect transistors which have very short channel lengths. A lightly doped semiconductor layer is deposited on an electrically insulating substrate. A gate insulator layer is applied onto which first and second gate electrodes are formed for the two transistors. A masking oxide layer is applied to the exposed surface regions of the gate insulating layer and the gate electrodes. An opening is etched into the masking layer and gate insulator layer lying adjacent each gate electrode. Charge carriers of first and second types are diffused through the respective openings into the region of the semiconductor layer lying below to dope the same. This doping extends partially into the semiconductor region lying beneath a portion of the respective gate electrodes. All parts of the gate insulator layer except those parts lying beneath the gate electrodes are removed. Charge carriers of the second and first type are diffused into the semiconductor layer on opposite sides of the first and second gate electrodes, respectively, while leaving a portion of the first and second doped regions unchanged beneath the first and second gate electrodes. The doped regions of the semiconductor layer on opposite sides of the first and second gate electrodes provide the source and drain regions of the first and second field effect transistors, respectively.

Plural control memory system with multiple micro instruction readout

Abstract: A microprogramming control system employing a plurality of low read rate control memories, for storing micro instructions, individually addressed in turn at a rate greater than the read rate of each memory. Each addressed control memory reads out a plurality of micro instructions. A selection circuit receives the plurality of micro instructions, in time shared fashion, read out in turn from each addressed control memory, then selects and gates a single micro instruction to a storage device. One portion of the selected micro instruction is designated as an address for the next micro instruction to be read out from the same control memory, and is accordingly gated to an address storage device at the input of the corresponding control memory.

Pulsed light source discriminator system

Abstract: A system sensitive to light pulses which are substantially synchronous with a selected pulsed light source containing frequency components within the pulse which are above a predetermined frequency. A signal for exciting the selected pulsed light source is frequency modulated and connected to an AND gate as well as to the pulsed light source device. The pulsed light is received and conditioned producing a received signal which is also connected to the AND gate. Gate output occurs only during the period of time the received signal is in time coincidence with the frequency modulated pulsed light source excitation signal. Additional light pulses transmitted in the immediate area of the receiver by additional light pulse transmitting devices having frequency components within the light pulse above the predetermined frequency may be sensed by the receiver, but will not produce output at the AND gate unless in time coincidence with the frequency modulated signal. An occasional pulse or several pulses from the additional light source may, by chance, fall partially in time coincidence with the frequency modulated signal thereby producing one or several AND gate outputs in sequence. A step-charging filter receives the AND gate outputs requiring a predetermined number of sequential AND gate outputs to reach a predetermined filter output signal level. Thus the frequency modulated signal and the received signal must be in time coincidence for the predetermined number of sequential received pulses before the charging filter produces an output which initiates the system output. In this fashion a plurality of proximate pulsed light sensitive systems may operate with each system having a unique instantaneous transmitted light pulse frequency modulated phase by which associated receivers may discriminate between light pulse sources.

Method for testing logic chips and logic chips adapted therefor

Abstract: Monolithic structures having high circuit density wherein the circuitry is arranged, and/or includes circuitry, to facilitate testing of said monolithic structure. Method for effectively and efficiently testing the circuits arranged and adapted for testing on a monolithic structure having high density. Namely, a test method for testing logic chips and logic chips adapted to be tested by said test method. A test method is disclosed wherein the logic chip, or monolithic structure, is arranged, or divided, into functional subassemblies, or logic locks, exhibiting a high degree of testability and includes integrated decoding means allowing individual sub-assemblies to be selected. The decoding means further allow a test pattern applied thereto to be transferred to the selected sub-assembly. Transfer means are provided between the sub-assemblies so as to isolate them electrically from one another during the test operations. The output pattern provided by a sub-assembly in response to the input test pattern applied thereto is applied to gating means which allow all output patterns to be fed to a single output pin. The above abstract is not to be taken either as a complete exposition or as a limitation of the present invention, the full nature and extent of the invention being discernible only by reference to and from the entire disclosure.

Binary parallel adder employing high speed gating circuitry

Abstract: In a binary parallel complementing L.S.I. adder, a C-MOS transmission gate is provided in each stage with its input and output directly connected to the carry in and carry out leads of the stage. The gate is switched by complementary control bits derived by stage input logic operating on the bits to be summed, whereby very fast passage of a carry through the stages is achieved. The transmission gate consists of p- and n- channel MOS transistors with their sources connected in common to the input and their drain electrodes likewise connected in common to the output.

Method and apparatus for controlling synchronous motor

Abstract: In the control of a synchronous motor driven by a power converter of voltage source type, the phase of the current flowing into the motor is detected and gate signals are produced on the basis of the phase of the current, so that the output frequency of the power converter is controlled by the gate signals so as to control the motor.

High speed multiplier logic circuit

Abstract: A 4 × 4 multiplier uses four bit threshold logic type adders. The multiplier per se is arranged in a carry save configuration with first level pseudo type carry-look ahead with the highest weight bit of the product being accomplished by a wired OR connection. The four bit adder itself provides two double threshold detectors responsive to logic levels provided by a level shifter which shifts the logical voltage levels produced by a differential amplifier which sums the four inputs of the adder circuit. This provides the sum output; an additional double threshold detector provides the first carry output and a typical threshold AND gate the second carry output.

Symmetric output, digital by three counter

Abstract: A digital divide by three ( divided by 3) counter providing a symmetrical square wave output waveform from a square wave input signal utilizing digital logic devices. The circuitry includes a conventional divide by three digital counter whose nonsymmetrical square wave output is fed to one input of an AND gate and to one input of a delay type flip-flop circuit after being fed through a logic inverter. The square wave input fed to the counter is additionally fed to the other input of the AND gate and the delay type flip-flop, whereupon the output of the AND gate and flip-flop are fed to an OR gate whose output comprises the desired symmetrical waveform.

A Note on Easily Testable Realizations for Logic Functions

Abstract: It is shown that at most, n + 3 tests are required to detect any single stuck-at fault in an AND gate or a single faulty EXCLUSIVE OR (EOR) gate in a Reed-Muller canonical form realization of a switching function.

Transmission shifting control system

Abstract: A bistable memory circuit is set by a first output signal produced when the driver is absent from his seat of the vehicle to produce an output signal and is reset by a second output signal produced when the driver sits down on his seat but fails to carry out a precautionary safety procedure to protect him to cease to produce the output signal. An AND gate circuit produces an output signal only when an output signal produced when the driver sits down on his seat and the output signal of the bistable memory circuit are concurrently present. An OR gate circuit produces an output signal when at least one of the second output signal and the output signal of the AND gate circuit is present to energize a solenoid to render shifting of the transmission from a parking or neutral position into a driving gear impossible.

Periodic pulse check circuit

Abstract: An error checking circuit for checking periodic pulses for the absence of a pulse or the presence of a spurious pulse. A sequence of periodic pulses is passed through an inverter gate delay line having outputs available from each gate in the delay line. The outputs from even-numbered gates are connected to the inputs of a first gate whose output is a missing pulse error signal when that condition exists. The outputs from odd-numbered gates are connected to the inputs of a second gate whose output is a spurious pulse error signal when such a pulse occurs. Memory means are also provided to store the two output signal conditions.

Coded counting sequence and logic implementation thereof to drive a display pattern

Abstract: An integrated circuit is disclosed providing the logic to generate a unique binary coded numerical counting sequence and a corresponding decoded segment select sequence to subsequently activate particular segments comprising a display pattern at predetermined times. A minimum number of logic input terms and respective logic gates are required to implement the instant sequence to thereby reduce the space consumed by the circuit and the cost thereof.

Serial two{3 s complementer

Abstract: The present invention relates to a serial two''s complementer whose logical design, by the preferential use of NAND devices and other measures, provides a minimum geometry configuration, in an implementation using metal oxide semiconductor field effect transistors with large scale integration. The two''s complement function is achieved by a binary storage element implemented by an inverter, two NAND gates with two half bit dynamic delays and by an exclusive NOR gate implemented by a NAND gate and a composite NAND-OR configuration. The binary storage element and exclusive NOR gate are interconnected to invert the serial bit stream after the occurrence of the first one to produce the two''s complement.

Checking circuit for a 1-out-of-n decoder

Abstract: A checking circuit for a 1-out-of-n decoder and a method of the designing thereof is disclosed. The method involves generating a binary table of n rows, 0 through n-1, each row comprising a set of K, 0 or 1, entries, and K columns, 0 through K-1, with a 0 or a 1 entry at each row-column intersection. Associating each of the n sets of entries with an associated one of the n outputs of the decoder, the 0 entries and the 1 entries of each column are coupled to separate pairs of column-associated 0-OR gates and 1OR gates, respectively. The output of each of the pairs of column-associated OR gates are then coupled to a separate columnassociated AND gate, the outputs of which are coupled to a >1-OR gate for indicating that two or more of the decoder outputs are active. The outputs of a pair of column-associated OR gates are coupled to a <1-OR gate for indicating that none of the decoder outputs is active.

LSI microprocessors and microprograms for user-oriented machines

Abstract: The fundamental aspect of microprogramming as introduced by Wilkes in 1951 [1,2] is the implementation of sequential control with stored or programmed logic in contrast to hardwired random logic involving adhoc connections of large numbers of simple logic gates. The microprogramming became practical with the availability of high speed memories at reasonable cost during the 60s and has become a very popular tool even for the design of small, low-cost computers. [3,4],Now steadily improving performance of LSI memories at declining cost and availability of LSI functional components to implement combinatorial and sequential logic functions tend to obliterate the classic distinction between logic and memory based on old technologies, i.e., electronic logic and magnetic memory with incompatible speeds, signal levels, and power requirements. Although we still do have minor incompatibilities between TTL and MOS signal levels, these are bang eliminated with introduction of NMOS (N-channel Metal Oxide Semiconductor) LSI devices which are fully TTL compatible. The full compatibility of memory and logic at hardware level, and availability of LSI memories and processing elements in convenient sizes, speeds and capacities at a steadily declining cost seem to favor use of programmed logic over hardwired random logic in many old and new applications, just as the microprogramming has been favored over hardwired logic for the design of control unit.This technological development provides the computer architect and digital system designer with new freedom to distribute “intelligent, programmable” chips throughout his system from the control processor within a central processor to “dumb” peripheral devices. This unprecedented design freedom seems to be the most significant aspect of LSI technology that the designer must realize before he can bring its benefits to users.This paper attempts to explore potentials and limits of LSI technology, and its profound implications for microprogramming, computer design, and computer usage.

Address selection circuit for storage arrays

Abstract: For each binary position of the coded addresses the selection device shows a phase splitter whose two outputs are connected to associated inputs of decoders. In order to increase the noise resistance jointly clocked AND gates are inserted at the inputs and outputs of the phase splitters, and at the outputs of the decoders. An automatic optimum determination of the conditioning time of the AND gates at the outputs of phase splitters is achieved by a delayed clock pulse DCS1 derived from a clock pulse T of AND gates at the input of the phase splitters. For that purpose, clock pulse T is derived at the output of the AND gates at the input of phase splitters and, via a simulated phase splitter circuit integrated on the chip, is applied as clock pulse DCS1 to the clock inputs of the AND gates at the output of the functional phase splitters. The determination of the conditioning time of AND gates at the output of the decoder is performed accordingly at the output of decoder. In that process, a clock signal is derived from the output of AND gates at the output of phase splitters, and applied as a delayed clock signal DCS2 via a simulation of one of decoders to the clock inputs of the AND gates at the output of the decoders.

Binary universal flip-flop employing complementary insulated gate field effect transistors

Abstract: A universal J-K flip-flop is implemented with insulated gate field effect transistors of both P and N channel types. The transistors are interconnected as a plurality of AND gates and NOR gates, with some transistors serving a dual function in both the master and slave portions of the flip-flop. A provision for direct set and reset of the flip-flop also is included.

Optical logic

Abstract: We report the theory and experimental demonstration of a laser device which performs the functions of binary arithmetic optically. Completely optical processing of logic functions could constitute a significant breakthrough in speed over conventional electronic processing. In our approach, input light pulses are assigned a binary code (0 or 1) according to their polarization along one of two mutually orthogonal directions. The response of the system to inputs of pairs of pulses consists of a pulse polarized along one of these initial orthogonal directions. The output pulse polarization can be made to correspond to those of the truth table for any of the logic operations of Boolean algebra. We report here achievement of the optical AND gate.

Gate generator with J-K flip-flops

Abstract: A gate generator including first and second JK flip-flops each having inhibit, J, K, and drive inputs. The inhibit inputs are also commonly known as the set and reset inputs. It is common to refer to the outputs of the flip-flops as the Q and Q outputs. A D.C. source of potential is provided from which a resistor is connected to each J input. Both K inputs are connected to ground. A source of pulses is also provided. Both clock inputs are connected from the pulse source. A NAND gate having first and second inputs and an output has the Q output of the first flipflop connected to the NAND gate first input. The Q output of the second flip-flop is connected to the NAND gate second input. The second flip-flop Q output is connected to the reset input and the first flip-flop. Manually operable means are then provided for momentarily changing the potential at the second flip-flop reset input to cause the Q output of the second flip-flop to be high.

Code translation arrangement

Abstract: The translation arrangement translates a pulse density modulation binary signal to a conventional pulse code modulation binary signal. The arrangement includes a digital filter to which a pulse density modulated signal is applied and logic means coupled to the output of the digital filter, the logic means being arranged to select every mth group of n pulses in the digital filter output.

Cage gate latch

Abstract: An integrally formed cage gate latch is provided having a unitary flat spring body structure with a serpentine S configuration. The convolutions of the cage gate latch form wire engaging loop portions which are adapted to make snap lock engagement with selected wires of cage and gate structures which are in close parallel register so as to maintain the gate in its closed position on a cage.

Real-time index register

Abstract: A counting-register whose enabling signal can be chosen from one of a group of synchronous frequencies for real-time measurement or from an incrementing signal from an iterative loop in a computer. This convertible register comprises two four-bit counters connected in series, an AND gate and a multiplexer to provide an enabling signal at one of the above-stated frequencies to the AND gate which applies the enable signal to the counters if the output from the last of the series counters is a one.

Quality control system for cigarette making machine - has strand density, length and weight signals combined to indicate substandard product

Abstract: Tobacco formed into a continuous strand is deposited onto a continuous paper strip which is gummed, folded around it and sealed. A weighing device is positioned after the knife which cuts the wrapped strand into cigarette lengths. When a button is pressed, a test pulse is emitted to an AND gate to actuate a valve to blow a determined number cigarettes into the weighing pan, and another AND gate operates a counter. Signals are also obtained from a strand density monitor employing beta rays from a Strontium 90 source, which pass into an evaluator with a pair of equalising arms followed by threshold value transmitters on an OR gate, flip flop, NOT gate, a shift register arrangement. These signals are combined with signals from the weighing system potentiometer.

Push-pull fluidic logic element and drive unit

Abstract: A fluidic logic element and drive unit is disclosed which performs the half adder logic function of a passive AND gate but has a single output capable of giving two distinct output signals. The element has opposed aligned input nozzles and diverters arranged so that an output port is pressurized by the simultaneous presence of input signals at each nozzle and is evacuated by an atomizer effect when an input is present at either nozzle alone. The AND signal is indicated by a pressure at the output, while the OR signal is indicated by a vacuum at the output.