Showing papers on "Arithmetic logic unit published in 1996"

Apparatus having a plurality of programmable logic processing units for self-repair

Abstract: An information processing apparatus with programmable function and self-repair function which can deal with multiple troubles the information processing apparatus includes a logic processing unit formed of logic forming elements for realizing a predetermined function; spare logic processing units that can be reconfigured of logic forming elements to reproduce the predetermined function of the logic processing unit; a data holding unit for holding forming data in the logic processing unit; a fault detecting unit for detecting a fault occurrence in the logic processing unit; and a reconfiguring unit for reconfiguring the spare logic processing unit having a logic circuit configuration similar to the logic processing unit, based on configuration data read out of the data holding unit, when the fault detecting unit detects a fault occurrence The information processing apparatus can automatically reconfigure the system to reproduce its original normal function of a faulty forming element

Carry chain circuit with flexible carry function for implementing arithmetic and logical functions

Abstract: An improved arithmetic logic unit (ALU) of an erasable-programmable logic device (EPLD) with a flexible, programmable carry function allows a broad range of functions to be implemented. The inventive circuit utilizes a separately configurable carry chain with multiple logic and arithmetic function capabilities.

Floating point processing unit with forced arithmetic results

Abstract: Logic for selectively forcing arithmetic results allows a floating point unit to bypass the normal flow through arithmetic units and pipelines depending on the particular floating point operation and operand conditions. Certain forced results (e.g., forced zeros, infinities, and those corresponding to certain invalid operand conditions) may bypass arithmetic units or pipelines and rounding circuitry entirely. On the other hand, other operand dependent results (e.g., the result of X + 0 and results of operations involving an NaN operand or operands) may only partially bypass the normal flow. By providing logic for selectively forcing results, arithmetic pipelines may be freed for subsequent instructions in the instruction stream. Logic for selectively forcing arithmetic results may be particularly attractive in a superscalar processor. In a superscalar processor which includes a floating point unit with forced arithmetic results, microcode to handle special cases, pipeline bypass, and early result generation can be avoided because architectural approaches for handling out-of-order results allow dependencies to be resolved irrespective of result reordering. Therefore, the early and out-of-order generation of forced results may be handled by a reorder buffer.

Arithmetic additive generators of pseudo-exhaustive test patterns

Abstract: Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme (Rajski and Tyszer, 1993) facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.

Image-processing processor

Abstract: The invention essentially concerns a matrix array of processor units, each processor unit having an arithmetic logic unit (ALU2) and a result-registering bank (REGF) as well as an additional arithmetic logic unit (ALU1), a multiplier/adder (MA), one storage unit (ISB) of a divided screen-section memory and a local general-purpose memory (GPM). The processor is characterized by its high data-processing speed for a small chip surface and makes real-time processing possible even with calculation-intensive image-processing techniques such as 2D-folding, Gabor transformation, Gauss or Laplace pyramids, block matching, DCT and MPEG2.

System for maintaining fixed-point data alignment within a combination CPU and DSP system

Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction When, in the data transfer between the digital signal processing unit and memories or external circuits, data shorter in bit length than the calculation precision is transferred, the calculation unit has a function to input and output data to and from the higher-order side of the register in which the data is stored and the fixed point data transfer instruction is provided separately from the conventional integer data transfer instruction This invention can eliminate additional correction processing necessitated when the integer data processing unit is made to execute the digitalsignal processing

Parallel-pipelined image processing system

Abstract: Apparatus for image processing a sequence of images containing a parallel-pipelined image processor comprised of image memories, a pyramid processing circuit, an arithmetic logic unit, a crossbar switch for video routing through the various components of the processor, signal processors to provide hardware programming through a global bus and also perform image processing operations. Images can be passed directly from the crossbar switch to internal static RAM of the signal processors through a first-in, first-out interface at full video rates.

Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Power comparisons for barrel shifters

Abstract: Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of mobile computing, power has become as important as speed for circuit designs. In this paper we present a power-delay analysis for a range of 32-bit barrel shifters that vary at the gate, architecture, and environment levels.

Applications of random-pulse machine concept to neural network design

Abstract: Neural networks can reach their true potential only when they are implemented in hardware as massively parallel processors. This paper presents the random-pulse machine concept and shows how it can be used for the modular design of neural networks. Random-pulse machines deal with analog variables represented by the mean rate of random-pulse streams and use simple digital technology to perform arithmetic and logic operations. This concept presents a good tradeoff between the electronic circuit complexity and the computational accuracy. The resulting neural network architecture has a high packing density and is well suited for very large-scale integration (VLSI). Simulation results illustrate the performance of the basic elements of a random-pulse neuron.

Data processing condition code flags

Abstract: A data processing system incorporating an arithmetic logic unit (20, 22, 24) having an N-bit data pathway and supporting parallel operation program instruction words in which to independent arithmetic operations are carried out in parallel by the arithmetic logic unit upon (N/2)-bit input operand words. Two sets of condition code flags N, Z, C V, SN, SZ, SC, SV responsive to the separate arithmetic logic operations are provided.

Bit processing unit for performing complex logical operations within a single clock cycle

Abstract: A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.

A dual floating point coprocessor with an FMAC architecture

Abstract: The CPU chip is implemented in a 5-layer metal 0.5 /spl mu/m CMOS process and delivers >360 SPECint92 and >550 SPECfp92. It is an out-of-order super-scalar processor with two integer, two floating point, two shift/merge and two load/store units. This paper describes circuits in the floating-point unit of this CPU.

Input operand size and hi/low word selection control in data processing systems

Abstract: A data processing system having a plurality of registers 10 and an arithmetic logic unit 20, 22, 24 includes program instruction words having a source register bit field Sn specifying one of the registers storing an input operand data word together with an input operand size flag indicating whether the input operand has an N-bit size or (N/2)-bit size together with a high/low location flag indicating which of the high order bit positions or low order bit positions stores the input operand if it is of the smaller size. It is preferred that the arithmetic logic unit is also able to perform parallel operation program instruction words operating independently upon (N/2)-bit input operand data words stored in respective halves of a register.

Hardware check of arithmetic devices with abridged execution of operations

Abstract: There is propound the check by modulo method of multiplier with the abridgement of computation, that is in high-performance floating-point arithmetic devices. The forming of uncalculated part of the operation result by processing of small capacity check codes of the operands and their parts is on the basis of the method. It provides simplicity of the check circuit for which equipment expenses are in linear depending on the capacity of operands under condition squaring dependence of expenses of the main equipment.

Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction

Abstract: A microprocessor circuit is disclosed for instructions on an arithmetic/shift function performing standard operations (e.g., ALU instructions or Shift instructions) on instructions in a first cycle of operation, and a correction circuit responsive to the arithmetic/shift function for modifying the standard results provided by the arithmetic/shift function to results required by a SIMD instruction being executed. The arithmetic/shift function is an instruction provided by either an Arithmetic Logic Unit (ALU) or by a shift instruction. The correction circuit passes data, unchanged for logical instructions but provides condition codes according to the SIMD instruction.

Method and apparatus for performing a masked byte addition operation

Abstract: A method and apparatus for performing an add-masked byte operation on a word of digital data comprises a register for receiving the word, a register for receiving a mask byte, and a multiplication module for receiving inputs from the registers A multiplier multiplies each byte in the word by a corresponding bit in the mask byte to obtain a series of partial products A multiplexer shifts the partial products until the partial products are disposed in the same register location as the location of the partial product achieved with the least significant byte in the word An arithmetic logic unit clears certain bits in the partial products and adds the partial products to obtain a sum The use of an existing multiplier module in an image processing system eliminates the costs involved in providing additional hardware for performing an add-masked byte operation

Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers may be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, an arithmetic logic unit may be partitioned into at least two logic portions. A first logic portion may be coupled to receive a first operand from a fixed slot of a first register and a second operand from any slot of a second register. A second logic portion may be coupled to receive a third operand from a fixed slot of the first register and a fourth operand from any slot of the second register. The first logic portion may perform an arithmetic operation dissimilar from the second logic portion.

Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unit

Abstract: An apparatus, a processor, a computer system and a method may be used to directly transfer and translate data between a memory format in an integer processing unit and a floating point format in a floating point processing unit. Data is stored in integer registers of the integer processing unit in a memory format and is stored in floating point registers of the floating point processing unit in a floating point format. A direct data link is provided between the integer register file of the integer processing unit and the floating point register file of the floating point processing unit. The direct data link includes a logic circuit which translates data between the memory format and the floating point format.

Method and apparatus for improving timing accuracy of a semiconductor test system

Abstract: A semiconductor testing system that performs real-time adjustment of programmed values for test signals using an interface between a system controller and the pin resources. The interface includes a calibration memory that contains timing offset values and amplitude level offset and gain values. An arithmetic logic unit combines these compensation values with the programmed values. The compensated values are then sent to test system registers that control pin resources, such as pin electronics of the semiconductor testing system.

On-Chip I/sub DDQ/ testability schemes for detecting multiple faults in CMOS ICs

Abstract: In this paper we present two on-chip design-for-testability (DFT) schemes for CMOS ICs. One is for small circuits and the other for large circuits. Both schemes identify a faulty area on a chip with only a small area overhead for the additional circuitry and at most two extra pins. Moreover, if faults occur in different areas, multiple faults can also be detected with the proposed schemes. To demonstrate the ideas, DFT is incorporated in a 4-bit carry look ahead adder/subtractor (CLAAS) as well as a 16-bit arithmetic logic unit (ALU). Simulation results are given.

Design of a fast, easily testable ALU

Abstract: The design and implementation of a fast, easily testable arithmetic-logic unit (ALU) is described. It is built around an adder design which is level-testable (L-testable), implying that the number of test patterns required to detect all functional faults in modules grows logarithmically with the size of the ALU. L-testability is achieved by exploiting some inherent properties of carry-lookahead addition. The resulting ALU design requires only two extra inputs, regardless of the size of the ALU. For an 8-bit implementation that has little impact on performance, the area overhead is shown to be less than 9%.

Arithmetic logic unit with improved critical path performance

Abstract: An arithmetic logic unit (ALU) with improved critical path performance includes two sets of adder circuits, a logic circuit, a set of multiplexors and a decoder. The adder circuits perform redundant add operations, one with a unit carry input and one without a carry input, upon multiple respective portions of the two sets of input signal bits. The logic circuit performs Boolean logic operations upon the two sets of input signal bits. In accordance with a set of selection control signals, the multiplexors select among the multiple results of such redundant add operations and Boolean logical operations for outputting as the final output bits. Such selection control signals are generated by the decoder based upon the contents of the two sets of input signal bits.

An arithmetic unit

Abstract: There is disclosed an arithmetic unit which allows a combined multiply-add operation to be carried out in response to execution of a single computer instruction. This is particularly useful in a packed arithmetic environment, when a operand comprises a plurality of packed objects and the intention is to carry out the same arithmetic operation on respective pairs of objects in different operands. There is also provided a computer and a method of operating a computer to effect the combined multiply-add operation.

Pipelined data processing device having improved hardware control over an arithmetic operations unit

Abstract: An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein the instruction decoder controls the execution of the arithmetic operation unit according to the information stored by the state retaining unit. A state is set when the decoder issues a signal for starting the arithmetic operation unit and the state is cleared when the decoder issues a signal for stopping the operation of the arithmetic operation unit. The arithmetic operation unit further comprises a unit for obtaining a maximum and a minimum value with a simple construction. A multiplier of the arithmetic operation unit comprises a unit for performing an addition of an exponential part of a multiplier and that of a multiplicand with a simple construction. The arithmetic operation unit further comprises a data packing and unpacking unit for packing and unpacking vector data. The data processing device is divided into several units and scan paths are divided into several paths corresponding to respective units.

EXECUTION UNIT ARCHITECTECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING

Abstract: A microprocessor execution unit includes an arithmetic unit and an addressing unit. The arithmetic unit performs arithmetic and logical operations on operands. The addressing unit operates in conjunction with the arithmetic unit to calculate offsets, limits, and linear addresses in a single cycle.

Manipulation of boolean values and conditional operation in a microprocessor

Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers ("GPRs" 102) and an arithmetic logic unit ("ALU" 104), capable of performing arithmetic operations and comparison operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN) capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.

Method and device for performing modulo-based arithmetic operations in an asynchronous transfer mode cell processing system

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a modulo arithmetic feature which permits branching on the modulo portion of the result of an arithmetic operation. An arithmetic logic unit (ALU) or other processor instruction is modified to include a modulo field which specifies the number of right to left bits after which the result of the corresponding ALU operation will be truncated. Conditional branch instructions such as branch on zero result, branch on non-zero result, branch on negative result, branch on carry and branch on overflow may be configured to operate only on the modulo portion of the ALU instruction result and/or on a carry out of the most significant bit (MSB) position of the modulo portion.

A method for reducing the number of bits needed for the representation of constant values in a data processing device

Abstract: A method for reducing the number of bits needed to represent constant values in a data processing device. A group of constant values is defined by selecting them as a function of their statistical frequency of use. Each constant value of this group in the instructions is represented by means of a shorter coded operand field and a current instruction is loaded from a bus in an instruction register. A corresponding operand field is derived from the coded operand field of the current instruction by expansion means, and a bus and an output of the expansion means are selectively connected as input to an arithmetic logic unit.