Showing papers on "Asynchronous communication published in 1982"

Queueing Network Models for Parallel Processing with Asynchronous Tasks

Abstract: Computer performance models of parallel processing systems in which a job subdivides into two or more tasks at some point during its execution are considered. Except for queueing effects, the tasks execute independently of one another and do not require synchronization. An approximate solution method is developed and results of the approximation are compared to those of simulations. Bounds on the performance improvement due to overlap are derived.

Direct Implementation of Asynchronous Control Units

Abstract: The "one-hot" row assignment for asynchronous circuits, in which every row in a flow table has exactly one of the feedback variables that equals the value 1, provides a straightforward method for circuit synthesis. Once a flow table has been constructed, the state equations can be directly written, without requiring any procedure to ensure a race-free assignment. Furthermore, it can implement any arbitrary fundamental mode asynchronous circuit, not depending on a specific signaling protocol for its correct operation. An alternate view of one-hot asynchronous circuits is given, with a simple set-reset flip-flop for each state. Although this may seem excessive compared to implementations with encoded state variables, for many circuits their one-hot implementation is comparable in cost to other asynchronous implementations.

Data transfer network for variable protocol management

Abstract: A data transfer network uses an I/O subsystem to support a main host computer in managing data transfers to and from remote data terminals. The I/O subsystem may constitute one or more units called a Line Support Processor. The Line Support Processor uses internal processor means to control a plurality of line adapters each of which has a data-comm line to a data set or data terminal. Control operations by said internal processor permit selected line adapters to operate selected types of protocols using synchronous or asynchronous transmission. Data communication information and commands in high level language data are loaded into auxiliary memories in the internal processor means and into each line adapter where the internal processor means acts to convert this language data into usable protocols.

A synchronous approach for clocking VLSI systems

Abstract: Presents a synchronous solution for clocking VLSI systems organized as distributed systems. This solution avoids the drawbacks of the self-timed approach. These VLSI systems are constituted of modules which represent synchronous areas driven by their own fast clock, interconnected by a synchronous communication mechanism driven by a slow clock. In order to avoid the risk of metastability in flip-flop between the modules and the communication mechanism, the author suggests to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.

Random access memory having a second input/output port

Abstract: A semiconductor random access memory is provided having a second asynchronous input/output port. Block transfers of data can be effected to and from the memory using the second input/output port. Memory throughput efficiency is improved permitting functions such as display refresh in a mapped memory display to be accomplished through the second input/output port. Memory bus contention on the primary port is also relieved. The main input/output port is thereby free to receive new data for a higher percentage of available transfer time since refresh data is available at the second input/output port.

Method and apparatus for high speed asynchronous serial data transfer

Abstract: A method and apparatus for high speed asynchronous serial data transfer between two microprocessors. Each of the two microprocessors is coupled to an asynchronous receiver/transmitter having a request-to-send output and a clear-to-send input. Each asynchronous receiver/transmitter also has a wait/ready output for utilization in conjunction with direct memory access devices or processors. The wait/ready output of a first asynchronous receiver/transmitter is applied to a digital filter to remove transients therein and the filtered signal is then coupled to the clear-to-send input of a second asynchronous receiver/transmitter, enabling the second asynchronous receiver/transmitter to transmit data back to the first asynchronous receiver/transmitter.

Asynchronous and clocked control structures for VLSI based interconnection networks

Abstract: A central issue in the design of multiprocessor systems is the interconnection network which provides communications paths between the processors. For large systems, high bandwidth interconnection networks will require numerous 'network chips' with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiprocessor systems may vary in size. This paper is concerned with the question of timing control of such networks. Two approaches, asynchronous and clocked, are used in the design of a basic network switching module. The modules and the approaches are then modelled and equations for network time delay are developed. These equations form the basis for a comparison between the two approaches. The importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented.

Formal Specification and Verification of Distributed Systems.

Abstract: Computations of distributed systems are extremely difficult to specify and verify using traditional techniques because the systems are inherently concurrent, asynchronous, and nondeterministic Furthermore, computing nodes in a distributed system may be highly independent of each other, and the entire system may lack an accurate global clock

Interface apparatus and method for asynchronous encoding of digital television

Abstract: Digitally encoded (DPCM) NTSC video is transmitted in a standard T3 data format and rate via a transmit interface module. The module is subjected to inputs comprising DPCM encoded NTSC video, horizontal sync and a video sampling clock at 3f sc , where f sc is the color subcarrier frequency. The sampling clock is used to write the DPCM encoded video and horizontal sync into a buffer. The buffer is read out via a read clock which is a submultiple of the 44736 MHz T3 rate. To assist in receiver decoding, the video data is supplemented with horizontal sync indicating code words, which designate the start of each horizontal scan line. On detection of a horizontal sync word read out of the buffer memory, the read clock is inhibited for the insertion of the horizontal sync indicating code words. The T3 frame is also supplemented with two digitized audio channels, stuff indicators and a stuff opportunity slot as well as parity, frame and multiframe indicators and an alarm channel. The T3 frame also carries data indicating a relationship between the T3 clock and f sc . This is useful at the receiver for ensuring that f sc at the receiver will track f sc at the transmitter. In accordance with standard T3 operation, the frame comprises 56 85-bit words, 28 odd and 28 even. The first bit of each 85-bit word is a control bit. Substantially all of the odd words include a 4-bit digitized audio nibble. Exceptions are two unused 4-bit nibbles, a single 4-bit stuff opportunity nibble and a single 4-bit video sample. Each of the even words includes 21 4-bit video samples which can be either video samples or sync indicating code words.

Establishing and supporting data traffic in private branch exchanges

Abstract: Apparatus for facilitating the transport and switching of synchronous and asynchronous digital data signals presented by data terminal or data communication equipments to a voice switching network such as a PBX advantageously without the use of modems. The clock rate of the PBX user's digital data is multiplied by a variable factor to define a synchronous transmission clock rate on a data link between a pair of interfaces, one locally connecting to the data terminal or data communications equipment and the other appearing as a port of the PBX switching equipment. The higher rate on the data link permits both the digital data as well as a control channel to be provided. Variations in the data terminal or data communications equipment clock rate do not affect the control channel. Variations in the voice sampling rate of switching modules serving different groups of ports through which the digital data is transported are accommodated.

Synchronizing Large Systolic Arrays

Abstract: Parallel computing structures consist of many processors operating simultaneously. If a concurrent structure is regular, as in the case of a systolic array. it may be convenient to think of all processors as operating in lock step. This synchronized view, for example, often makes the definition of the structure and its correctness relatively easy to follow. However, large, totally synchronized systems controlled by central clocks are difficult to implement because of the inevitable problem of clock skews and delays. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for systolic arrays are proposed. In general, this paper represents a first step towards a systematic study of synchronization problems for large systolic arrays. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional systolic array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness in the synchronization scheme. This result cannot be extended to two-dimensional arrays, however--the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and "asynchronous" elements is proposed.

FIFO buffer to cache memory

Abstract: A minicomputer system is disclosed having a megabus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling the detection, decoding, storage and dispatching of data and instructions between the megabus and associated processors. The logic detects information addressed to its associated processors and synchronizes the transfers between the independently timed asynchronous processors and the units attached to the megabus.

Dual port access circuit with automatic asynchronous contention resolving capability

Abstract: Two microprocessors, which may be operating asynchronously, share a random access memory (RAM) array; that is, at any one moment of time, either microprocessor can seek access to the RAM but only one of them can actually gain access at a time. Priority of access to the RAM is controlled by a dual port contention-resolving access circuit which enables such access alternately to the two microprocessors when both are seeking (overlapping) access, subject to the stipulation when neither microprocessor is accessing the RAM that the very next access will be allocated by the circuit on a first-come first-served basis, and will be allocated to a preselected one of the microprocessors if both microprocessors will commence to seek access precisely at the same time.

Synchronous Versus Asynchronous Computation In Very Large Scale Integrated (VLSI) Array Processors

Abstract: This paper compares timing and other aspects of a synchronous and asynchronous square array of processing elements, fabricated by means of VLSI technology. Timing models are developed for interprocessor communications and data transfer for both cases. The synchronous timing model emphasizes the clock skew phenomenon, and enables derivation of the dependence of the global clock period on the size of the array. This 0(N**3) dependence, along with the limited flexiblity with regards to programmability and extendability, call for a serious consideration of the asynchronous configuration. A self timed (asynchronous) model, based on the concept of wavefront oriented propagation of computation, is presented as an attractive alternative to the synchronous scheme. Some potential hazards, unique to the asynchronous model presented, and their solutions are also noted.© (1982) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Real time resource allocation in distributed systems

Abstract: In this paper we consider a resource allocation problem which is local in the sense that the maximum number of users competing for a particular resource at any time instant is bounded and also at any time instant the maximum number of resources that a user is willing to get is bounded. The problem may be viewed as that of achieving matchings in dynamically changing hypergraphs, via a distributed algorithm. We show that this problem is related to the fundamental problem of handshake communication (which can be viewed as achieving matchings in a dynamically changing graph, via distributed algorithms) in that an efficient solution to each of them implies an efficient solution to the other. We provide real-time solutions to the resource allocation problem (that is, we give distributed algorithms with real time response). We make essential use of probabilistic techniques as first used by [Rabin, 80b], where processes are allowed to make independent probabilistic choices. On the other hand, no probability assumptions about the system behavior are made. One of our solutions assumes the existence of an underlying real-time handshake communication system, as described in [Reif, Spirakis, 81]. Our other solution is based on efficient synchronization by flag variables, which are written only by one process and read by at most one other process. The special case of equi-speed processes is first examined. Then we generalize to asynchronous processes. Applications are made to dining philosophers, scheduling and two-phase locking in databases.

Circular-queue structure

Abstract: Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also permits commands and data to be chained in the same queue. The apparatus permits multiple devices to be handled simultaneously. By monitoring the memory address which is being accessed by the minicomputer, the information retrieved from the memory by the microprocessor is selectively validated or invalidated.

Method and device for the asynchronous series communication of the multipoint type between a plurality of logic transceivers

Abstract: Messages including an interruption character (12), a character designating the address of the sendee (13), a character designating the address of the sender (14), characters containing the useful information of the message (15, 16), and an interruption character (17) are communicated between a number of transceivers on a network. Each transceiver has circuitry to prevent transmission for a predetermined time (18) after reception of a character on the network. After each character emission, the sender compares the signals detected on the network with the signals to be transmitted and, in case of difference, ceases the transmission and generates an interruption character. Further transmission is then inhibited for a random period of time for each transceiver. Asynchronous communication, without the need for encoded clock signals in the messages, thus can be carried out on the network.

Communication adapter circuit

Abstract: A communication adapter circuit (10) is connected to a processor through a data bus (12)and a control bus (14) Data and control signals are provided through the buses (12,14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24) Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10) From the control circuits (22, 24) the data is transmitted through a bi-directional serial line (44) to a dual modem switch (56) From the switch (56) the data is transmitted to either an EIA interface circuit (60) to a conventional modem or through a line (64) to an internal modem

Method and apparatus for the error-free synchronization of asynchronous pulses

Abstract: Method and apparatus for the error-free synchronization of asynchronous pulses through logical interconnection of the asynchronous pulses with clock pulses of constant frequency by means of a flip-flop, which includes comparing output voltages of the flip-flop with a predetermined threshold voltage for determining a metastable state of the flip-flop, and flipping the flip-flop into a third stable state until the next clock pulse appears if a metastable state is present, for preventing an evaluation of the output voltages of the flip-flop.

Measuring simultaneous events in a multiprocessor system

Abstract: In the hierarchically organized multiprocessor system EGPA, which has the structure of a pyramid, the performance of concurrent programs is studied. These studies are assisted by a hardware monitor (ZAHLMONITOR III), which measures not only the activity and idle states of CPU and channels, but records the complete history of processes in the CPU and interleaved I/O activities. The applied method is distinguished from usual hardware measurements for two reasons: it puts together the a priori independent event-streams coming from the different processors to a well ordered single event stream and it records not only hardware but also software events. Most useful have been traces of software events, which give the programmer insight into the dynamic cooperation of distributed subtasks of his program. This paper describes the measurement method and its application to the analysis of the behaviour of a highly asynchronous parallel algorithm: the projection of contour lines from a given point of view and the elimination of hidden lines.This work is sponsored by the Bundesminister fur Forschung und Technologie (German Federal Minister of Research and Technology).

Understanding and using asynchronous message passing (Preliminary Version)

Abstract: Message passing provides a way for concurrently executing processes to communicate and synchronize. In this paper, we develop proof rules for asynchronous message-passing primitives (i.e. “send no-wait”). Two benefits accrue from this. The obvious one is that partial correctness proofs can be written for concurrent programs that use such primitives. This allows programs to be understood as predicate transformers, instead of by contemplating all possible execution interleavings. The second benefit is that the proof rules and their derivation shed light on how interference arises when message-passing operations are used and on how this interference can be controlled. This provides insight into programming techniques to eliminate interference in programs that involve asynchronous activity. Three safe uses of asynchronous message passing are described here: the transfer of values, the transfer of monotonic predicates, and the use of acknowledgments.

Axiomatic verification to enhance software reliability

Abstract: Techniques that facilitate the design of reliable software are described. Two distinct phenomena that can cause execution of a program to deviate from its specifications are considered. The first is the failure of the computing system on which the program is running. When this occurs, the system might not be capable of following the instructions specified by the program. The second phenomenon is that the program is written so that it will not execute consistently with its specifications, even on a failure-free computing system. A methodology is presented for designing programs that can cope with failures in the underlying system. It is based on the notion of a fail-stop processor--a processor with well-defined failure mode operating characteristics. Axiomatic program verification techniques are extended for use in developing provably correct programs for such processors. The problem of meeting response time goals in light of failures is discussed. Lastly, the problem of implementing processors that, with high probability, behave like fail-stop processors is addressed. Programming logics have already been developed to reason about sequential programs, and parallel programs that use shared memory or synchronous message-passing. That work is extended to facilitate reasoning about programs that use asynchronous message-passing. Two benefits accrue from this. The obvious one is that partial correctness proofs can be written for concurrent programs that use such primitives. This allows such programs to be understood as predicate transformers, instead of by contemplating all possible execution interleavings--often an intractable task. The other benefit is that these proof rules and their derivation shed light onto how interference arises when message-passing operations are used, and how this interference can be controlled. In particular, disciplines that make asynchronous message-passing primitives simple and safe to use are explored. A partial correctness proof of the two-phase commit protocol illustrates the application of the new techniques. This protocol, widely used in database applications, ensures that a specified action is performed either at all sites in a distributed system, or at no site, despite failures.

Asynchronous parallel fixed point converter

Abstract: An electronic circuit is used as an asynchronous floating point converter to process data. Data words are received and processed by the floating point converter to produce processed output data. The function for processing is software selectable and may be accomplished rapidly since the electronic circuit is not a clocked device.

Method of transmitting messages between autonomous transceiver modules having independent clocks and internal synchronisation means

Abstract: The message transmission method in binary coded form, in asynchronous serial mode between autonomous transceiver modules having clocks and independent internal synchronization devices, applies to an organization in which the modules are linked together by a single line of transmission. The method according to the invention consists in applying to the transmission line a series of signals each corresponding to a state 0 or 1 of a digit of the message to be transmitted. Each signal has a determined duration depending on the state Z = 0 or U = 1 of the transmitted digit. The receiver recognizes the sequence of 0 or 1 of the transmitted message by measuring the duration Z / E and U / E of the signals received using the duration of a standard signal E transmitted at the same time time that the message by the sender. The invention applies in particular to the realization of the electrical functions of a motor vehicle.

Asynchronous Parallel Search in Global Optimization Problems

Abstract: A class of asynchronous parallel search methods is proposed in this paper in order to solve the global optimization problem on a multiprocessor system, consisting of several processors which can communicate through a set of global variables contained in a memory shared by all processors. The speed-up ratio and memory contention effects are experimentally analyzed for some algorithms of this class.