Showing papers on "Asynchronous communication published in 1988"

Performance models of statistical multiplexing in packet video communications

Abstract: Models and results are presented that assess the performance of statistical multiplexing of independent video sources. Presented results indicate that the probability of buffering (or delaying) video data beyond an acceptable limit drops dramatically as the number of multiplexed sources increases beyond one. This demonstrates that statistical or asynchronous time-division multiplexing (TDM) can efficiently absorb temporal variations of the bit rate of individual sources without the significant variations in reception quality exhibited by multimode videocoders for synchronous TDM or circuit-switched transmission. Two source models are presented. The first model is an autoregressive continuous-state, discrete-time Markov process, which was used to generate source data in simulation experiments. The second model is a discrete-state, continuous-time Markov process that was used in deriving a fluid-flow queuing analysis. The presented study shows that both models generated consistent numerical results in terms of queuing performance. >

Timestamps in Message-Passing Systems That Preserve the Partial Ordering

Abstract: Timestamping is a common method of totally ordering events in concurrent programs. However, for applications requiring access to the global state, a total ordering is inappro­ priate. This paper presents algorithms for timestamping events in both synchronous and asynchronous n1essage-passing programs that allow for access to the partial ordering in­ herent in a parallel system. The algorithms do not change the con1munications graph or require a central timestamp issuing authority.

Promises: linguistic support for efficient asynchronous procedure calls in distributed systems

Abstract: This paper deals with the integration of an efficient asynchronous remote procedure call mechanism into a programming language. It describes a new data type called a promise that was designed to support asynchronous calls. Promises allow a caller to run in parallel with a call and to pick up the results of the call, including any exceptions it raises, in a convenient and type-safe manner. The paper also discusses efficient composition of sequences of asynchronous calls to different locations in a network.

Fiber optic voice/data network

Abstract: An asynchronous, high-speed, fiber optic local area network originally developed for tactical environments with additional benefits for other environments such as spacecraft, and the like The network supports ordinary data packet traffic simultaneously with synchronous T1 voice traffic over a common token ring channel; however, the techniques and apparatus of this invention can be applied to any deterministic class of packet data networks, including multitier backbones, that must transport stream data (eg, video, SAR, sensors) as well as data A voice interface module parses, buffers, and resynchronizes the voice data to the packet network employing elastic buffers on both the sending and receiving ends Voice call setup and switching functions are performed external to the network with ordinary PABX equipment Clock information is passed across network boundaries in a token passing ring by preceeding the token with an idle period of non-transmission which allows the token to be used to re-establish a clock synchronized to the data Provision is made to monitor and compensate the elastic receiving buffers so as to prevent them from overflowing or going empty

An overview of the SR language and implementation

Abstract: SR is a language for programming distributed systems ranging from operating systems to application programs. On the basis of our experience with the initial version, the language has evolved considerably. In this paper we describe the current version of SR and give an overview of its implementation. The main language constructs are still resources and operations. Resources encapsulate processes and variables that they share; operations provide the primary mechanism for process interaction. One way in which SR has changed is that both resources and processes are now created dynamically. Another change is that inheritance is supported. A third change is that the mechanisms for operation invocation—call and send—and operation implementation—proc and in—have been extended and integrated. Consequently, all of local and remote procedure call, rendezvous, dynamic process creation, asynchronous message passing, multicast, and semaphores are supported. We have found this flexibility to be very useful for distributed programming. Moreover, by basing SR on a small number of well-integrated concepts, the language has proved easy to learn and use, and it has a reasonably efficient implementation.

Analysis of tuning of FDDI media access control protocol

Abstract: The fiber distributed data interface (FDDI) provides a 100 Mb/s communication system to interconnect computer and peripheral equipment using fiber optics as the transmission medium in a ring configuration. The performance of the FDDI media-access control (MAC) protocol, a timed-token protocol, is analyzed. The FDDI MAC priority mechanism supports two classes of traffic: synchronous and asynchronous. The focus is on the relationship between the FDDI MAC parameter settings, the ring configuration, and the performance of the asynchronous priority levels. A procedure to calculate estimates for the throughput of each asynchronous priority level over a range of frame-arrival rates is developed. Performance results are presented to demonstrate characteristics of the FDDI priority mechanism. A procedure is described that can be used to tune the FDDI parameters so that given performance objectives for the various priority levels are achieved. >

Access control system having centralized/distributed control

Abstract: The access control system according to the present invention provides for the centralized control of the system operating parameters, including all times, access codes, alarms, error messages, and pass-coded indications. The access control system communicates with a plurality of remote card readers, at which point the user enters a code to gain entry into the protected areas. The access control system according to the present invention selectively stores limited information at each card reader location, wherein access control is still maintained, even if the central data system becomes inoperative. Moreover, the communication between the central data system and the plurality of card readers includes data transfers through a plurality of subsystems, each having a data processing program therein. The system according to the present invention provides for efficient communication between asynchronous operating subsystems through the controlled use of a first-in-first-out (FIFO) data register pair. In this manner, each subsystem according to the present invention operates independently until a data transfer is initiated, causing the other operations to be suspended to permit the transfer of data. The FIFO allows for data to be transferred at different rates between subsystems, allowing freedom in subsystem operation and data transfer rates.

Dual coordinate step methods for linear network flow problems

Abstract: We review a class of recently-proposed linear-cost network flow methods which are amenable to parallel implementation. All the methods in the class use the notion of c-complementary slackness, and most do not explicitly manipulate any "global" objects such as paths, trees, or cuts. Interestingly, these methods have also stimulated a large number of new serial computational complexity results. We develop the basic theory of these methods and present two specific methods, the E-relaxation algorithm for the minimum-cost flow problem, and the auction algorithm for assignment problem. We show how to implement these methods with serial complexities of O(N 3 log NC) and O(NA log NC), respectively. We also discuss practical implementation issues and computational experience to date. Finally, we show how to implement e-relaxation in a completely asynchronous, "chaotic" environment in which some processors compute faster than others, some processors communicate faster than others, and there can be arbitrarily large communication delays.

Advanced real-time scheduling using the IEEE 802.5 token ring

Abstract: An approach for scheduling the IEEE 802.5 token ring for hard real-time applications is presented that not only guarantees deadlines for synchronous class messages, but also greatly reduces asynchronous class response times. Highly responsive guaranteed service is introduced for alert class asynchronous messages. Conventional use of the IEEE 802.5 token ring provides synchronous communication services using time-domain multiplexing (TDM) while relegating asynchronous class message services to background status. An algorithmic-based scheduling approach is presented that supports a priori schedulability determination for arbitrary synchronous message sets without the costly time-line development, testing, and tuning associated with TDM techniques. This capability allows the IEEE 802.5 to support dynamic, adaptive and reconfigurable run-time environments where the inflexibility of TDM would be prohibitive. Advanced real-time scheduling applied to the IEEE 802.5 token ring greatly enhances the responsiveness of asynchronous class messages while still maintaining guaranteed service for the synchronous class. >

A new interface specification methodology and its application to transducer synthesis

Abstract: In this dissertation, I present a new methodology for the abstract specification of digital circuit interfaces. An interface is the collection of signal wires that cross a circuit boundary and the constraints on the events on those wires. The specification methodology is based on a formalization of the timing diagrams commonly used by digital circuit designers. This mostly graphic method is not only familiar to its intended users but is also concise in its description. An interactive editor, called Waves, has been implemented to support this methodology and used to describe a wide range of circuit interfaces ranging from static memories, to microprocessors, to system busses. Interface specification has a wide range of uses during the design and evaluation of a circuit. Waves diagrams and the constraints they capture form the basis for an entire new set of CAD tools that reason about interface design, synthesis, evaluation, and testing. One of these applications, the automatic synthesis of interface transducers, is highlighted in this dissertation. An interface transducer is the collection of logic circuitry that connects two compatible circuit interfaces. In general, it includes both synchronous and asynchronous components and must satisfy the timing constraints of both interfaces. Interface transducers are required whenever a custom chip is integrated into a computer system or in general, whenever two circuit blocks need to be connected. Their automatic design can greatly reduce the time required to assemble systems or integrate new components into existing systems. Janus uses a novel approach, based on a small set of templates, to synthesize mixed asynchronous and synchronous control logic. The synthesis algorithm, called Suture, first constructs a skeletal circuit and then locally modifies the design to meet interface timing constraints and eliminate internal race conditions. Optimizations of the resulting sequential logic yield transducers that are comparable in both size and performance to those generated by experienced designers. Three practical examples are used to demonstrate this result.

Method and apparatus for the continuous and asynchronous traversal and processing of graphics data structures

Abstract: A host system executes one or more application programs which results in graphic data structures. These graphic data structures are then continuously and asynchronously traversed. Traversal requests by competing application programs are scheduled and performed so that each application views the graphics processing as its own. The traversal and ordering of traversal requests provide efficient use of resources for multiple application programs.

Recovery in distributed systems using asynchronous message logging and checkpointing

Abstract: In a distributed system using message logging and checkpointing to provide fault tolerance there is always a unique maximum recoverable system state regardless of the message logging protocol used The proof of this relies on the observation that the set of system states that have occurred during any single execution of a system forms a lattice with the sets of consistent and recoverable system states as sublat tices The maximum recoverable system state never decreases and if all messages are eventually logged the domino e ect cannot occur This paper presents a general model for reasoning about recovery in such a system and based on this model an e cient algo rithm for determining the maximum recoverable sys tem state at any time This work uni es existing ap proaches to fault tolerance based on message logging and checkpointing and improves on existing methods for optimistic recovery in distributed systems

Method and apparatus for providing high speed parallel transfer of bursts of data

Abstract: Method and apparatus for high speed parallel transfer of bursts of data between a device and an external interface bus. A burst mode asynchronous protocol is utilized, in which synchronous bursts of data using DATA VALID signals are followed by an asynchronous handshake using an ACKNOWLEDGE signal. The apparatus includes a burst register for storing and transmitting the data words in a burst, and control logic responsive to DATA VALID and ACKNOWLEDGE signals and providing control signals to operate the burst register.

Parallel logic simulation on general purpose machines

Abstract: Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors. >

Performance prediction and calibration for a class of multiprocessors

Abstract: A model for predicting multiprocessor performance on iterative algorithms is developed. Each iteration consists of some amount of access to global data and some amount of local processing. The iterations may be synchronous or asynchronous, and the processors may or may not incur waiting time, depending on the relationship between the access time and processing time. The effect on performance of the speed of the processor, memory, and the interconnection network is studied. The model also illustrates the significant impact on performance of decomposing an algorithm into parallel processes. The model's predictions are calibrated with experimental measurements. >

An experimental 1-Mbit CMOS SRAM with configurable organization and operation

Abstract: A 1-Mb SRAM (static random-access memory) configurable as a 128-kb*8, 256-kb*4, or 1-Mb*1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7- mu m geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 mu m/sup 2/. >

A New Interface Specification Methodology and

Abstract: In this dissertation, I present a new methodology for the abstract specification of digital circuit interfaces. An interface is the collection of signal wires that cross a circuit boundary and the constraints on the events on those wires. The specification methodology is based on a formalization of the timing diagrams commonly used by digital circuit designers. This mostly graphical method is not only familiar to its intended users but is also concise in its description. An interactive editor, called Waves, has been implemented to support this methodology and used to describe a wide range of circuit interfaces ranging from static memories, to microprocessors, to system busses. Interface specification has a wide range of uses during the design and evaluation of a circuit. Waves diagrams and the constraints they capture form the basis for an entire new set of CAD tools that reason about interface design, synthesis, evaluation, and testing. One of these applications, the automatic synthesis of interface transducers, is highlighted in this dissertation. An interface transducer is the collection of logic circuitry that connects two compatible circuit interfaces. In general, it includes both synchronous and asynchronous components and must satisfy the timing constraints of both interfaces. Interface transducers are required whenever a custom chip is integrated into a computer system or in general, whenever two circuit blocks need to be connected. Their automatic design can greatly reduce the time required to assemble systems or integrate new components into existing systems. Janus uses a novel approach, based on a small set of templates, to synthesize mixed asynchronous and synchronous control logic. The synthesis algorithm, called Suture, first constructs a skeletal circuit and then locally modifies the design to meet interface timing constraints and eliminate internal race conditions. Optimizations of the resulting sequential logic yield transducers that are compatible in both size and performance to those generated by experienced designers. Three practical examples are used to demonstrate this result.

Performance analysis of slotted ring protocols in HSLANs

Abstract: The performance of a number of slotted-ring protocols supporting integration of synchronous and asynchronous traffic in high-speed local area networks (HSLANs) is evaluated. They are the Cambridge fast ring, a variant of the Cambridge fast ring, and Orwell. The performance of their basic access mechanisms is compared and contrasted with that of the multiple-token ring. The effect of a uniframe scheme for supporting synchronous traffic is examined. A delay analysis of the integrated-services slotted-ring protocols is presented. >

Asynchronous communication system

Abstract: Methodology, and associated circuitry, for encoding and decoding signals utilize combined time-signal path diversity techniques that trade-off bandwidth for autonomy of communications and simplified signal processing, thereby improving reliability. Transmitter (800) processes an incoming data stream by partitioning the stream into contiguous blocks. Each block is encoded into a data frame for transmission over one or more paths comprising the medium interconnecting the transmitter and receiver. Frame encoding is effected by generating an array of pulses distributed in time as well as distributed across the paths. Receiver (100) is generally arranged as a correlation detector in that the receiver only responds to the particular time-signal path pattern for which it is configured. Sensors in energy transfer relation to the one or more paths are positioned at detection points on the paths in correspondence to the time-space pattern of the receiver. The outputs of the sensors are processed to produce a correlation signal at the given frame rate whenever the coded signal corresponding to the receiver configuration is propagating along the paths.

Asynchronous time division communication system

Abstract: Asynchronous time division communication system wherein user stations (US1/2), each with an associated send and receive circuit (SEND1/2, REC1/2), are coupled with a packet switching network (PSN). Each send circuit includes a send clock (OSC) and each receive circuit is provided with a receive clock (POSC), controlling the reading of a packet buffer circuit (PFIFO), and with a computer (COMP) which regulates the receive clock (POSC) in such a way that the filling level of the buffer circuit remains substantially constant.

Method and apparatus for detecting a rate of data transmission

Abstract: An asynchronous interface for coupling data between a terminal and a data module is provided. The asynchronous interface directly determines and matches to the rate of serial data being transmitted by the terminal and received by the data module with minimal involvement of a processor associated with the data module. The asynchronous interface determines the rate of the data being transmitted by configuring counting circuitry therein for measuring the period of the start bit in the first received character whenever the speed of data being transmitted by the terminal must be determined. The asynchronous interface then adjusts to the newly determined data rate and receives the remaining bits in the first character and subsequent characters at the new rate. The processor is involved only to request that the asynchronous interface determine the incoming data rate and match to it and, once the data rate has been determined and matched, to process the recovered characters and this new rate. While the asynchronous interface determines and matches to the incoming data rate, the processor is freed for other tasks.

Highly responsive real time token rings

Abstract: The real-time communications problem is distinguished from the standard nonreal-time problem by the introduction of time. In the nonreal-time setting, it is sufficient to verify the functional correctness of a communications solution along with some notion of aggregate throughput and/or average delay. In the real-time setting, the individual message-level timing requirements are an integral part of the functional correctness. The current state of the art and predominant practice of using Time Domain Multiplexing (TDM) techniques to insure timing correctness tends to result in ad hoc, handcrafted timing solutions which are very hard to modify, upgrade and extend. Further, the deadlines of synchronous communications are guaranteed by relegating asynchronous class messages to a noninterfering, background status. This approach often results in poor system responsiveness. This thesis develops a novel approach for scheduling the IEEE 802.5 and SAE-9B token ring LANs for hard real-time applications that not only guarantees deadlines for synchronous messages, but also dramatically reduces the asynchronous messages' response times. Highly responsive guaranteed service is introduced for alert class asynchronous messages. This algorithmic-based scheduling approach supports a priori determination of system timing correctness for arbitrary synchronous and asynchronous message sets without the costly time-line development, testing and tuning associated with TDM techniques. This capability allows token rings to support dynamic, adaptive and reconfigurable run-time environments. In addition, a new Enhanced Responsiveness Protocol that directly embeds real-time scheduling theory into the media access protocol is developed that offers higher performance than is possible with standard-based methods. These new approaches introduce guaranteed alert class service, and dramatically enhanced asynchronous class message service to LANs. The result is highly responsive real-time rings that can form the backbone of predictable, stable extensible real-time systems.

Asynchronous multiphase switching gear

Abstract: An asynchronous multiphase switching method and apparatus are disclosed which transfers a system load between two asynchronous AC power sources in an improved manner. It operates as a make-before-break switch to provide uninterrupted power to the system load during the transfer while minimizing voltage and current fluctuations. The control circuitry allows energy to be supplied to the load during the transition without allowing current to flow between the power sources. A matrix of SCRs is used to transfer the load between the two power sources. The switches to be gated are determined by the relative timing relationships of the existing and takeover voltage waveforms. By altering the pattern of the switches which are gated and by controlling the direction of energy flow, the transition can be made between the power sources without interruption of power.

A compiler that increases the fault tolerance of asynchronous protocols

Abstract: A compiler that increases the fault tolerance of certain asynchronous protocols is presented. Specifically, it transforms a source protocol that is resilient to crash faults into an object protocol that is resilient to Byzantine faults. The compiler simplifies the design of protocols for the Byzantine fault model because it allows the design process to be broken in two steps. The first step is to design a protocol for the crash fault model. The second step, which is completely mechanical, is to compile the protocol into one for the Byzantine fault model. The compiler is used to produce an asynchronous approximate agreement protocol that operates in the Byzantine fault model and improves in several respects on the performance of the asynchronous approximate agreement protocol of D. Dolev et al. (1986). >

Apparatus for reconstructing and multiplexing frames of various origins made up of a variable number of packets of fixed length

Abstract: The apparatus is designed to use a single transmission medium to multiplex frames consisting of any number of bits of different origins which have previously passed through an asynchronous time-division network and are delivered in the form of packets of fixed length interlaced by an asynchronous time-division multiplex. A detection and write management circuit receives the packets and writes them in a packet memory as and when they arrive. In parallel with the writing of the packets, the addresses of the memory cell having memorized the packets of a given frame are written in the form of a string of frame addresses in a second memory. After complete writing of a frame in the first memory, a frame read and transmission circuit completely reads the frame using the corresponding address string and transmits it in serial form on the transmission medium. Packing words such as flags are inserted between the frames read.

Asynchronous-to-synchronous digital data multiplexer/demultiplexer with asynchronous clock regeneration

Abstract: Digital data received at asynchronous rates on input channels (10a to 10n) is multiplexed and transmitted by way of synchronous channels (150) together with encoded information of the original respective asynchronous rate. Data received form the synchronous channels is demultiplexed and clocked out on a respective output channel (182a - 182n) at a rate which is reconstituted from the encoded rate information for the respective data.

System and process for controlling the flow of either data packets or channel signals in an asynchronous time multiplexer

Abstract: A system and process for controlling the flow of packets carried by asynchronous time multiplex (EPACi) channels. The packets from one communication link are identified by their label and the identity of the multiplex channels which carries them. The process is comprised of allocating for each communication a predetermined clock rate and a predetermined threshold value, measuring the difference between the number of packets entering belonging to the communication and the number of pulses generated by the clock, lower bounding this difference, and, if the difference reaches a predetermined threshold, triggering a signal (DEP) which causes the detection of packets belonging to the communication in question as long as the difference is not less than the predetermined threshold. The signal (DEP) is used by the control means of a switch (XPAC) which transmits to the source of the communication in question a message requesting it to reduce its rate, when this is possible, and, in any event, a message warning it of a loss of packets.

Communication performance in multiple-bus systems

Abstract: A simple queueing model is presented for studying the effect of multiple-bus interconnection networks on the performance of asynchronous multiprocessor systems. The proposed model is suitable for systems in which each processor has a local memory and is thus able to continue processing while waiting for a response from the global memory. An approximate, closed-form solution is given that is simple and easy to use for any number of processors, buses, or memory modules and for arbitrary memory block size. The model is used to study the access time of the global memory as a function of the number of buses for different local-memory/global-memory traffic rates. >

The Use of Efficient Broadcast Protocols in Asynchronous Distributed Systems

Abstract: Reliable broadcast protocols are important tools in distributed and fault-tolerant programming They are useful for sharing information and for maintaining replicated data in a distributed system However, a wide range of such protocols has been proposed These protocols differ in their fault tolerance and delivery ordering characteristics There is a tradeoff between the cost of a broadcast protocol and how much ordering it provides It is, therefore, desirable to employ protocols that support only a low degree of ordering whenever possible This dissertation presents techniques for deciding how strongly ordered a protocol is necessary to solve a given application problem We show that there are two distinct classes of application problems: problems that can be solved with efficient, asynchronous protocols, and problems that require global ordering We introduce the concept of a linearization function that maps partially ordered sets of events to totally ordered histories We show how to construct an asynchronous implementation that solves a given problem if a linearization function for it can be found We prove that in general the question of whether a problem has an asynchronous solution is undecidable Hence there exists no general algorithm that would automatically construct a suitable linearization function for a given problem Therefore, we consider an important subclass of problems that have certain commutativity properties We present techniques for constructing asynchronous implementations for this class These techniques are useful for constructing efficient asynchronous implementations for a broad range of practical problems

Concurrent common knowledge: a new definition of agreement for asynchronous systems

Abstract: In this paper we discuss a new knowledgetheoretic definition of agreement appropriate to asynchronous systems. This definition has two important features; first, it uses causality rather than time in its definition and, second, this form of agreement is attainable. In analogy with common knowledge, it is called concurrent common knowledge. Concurrent common knowledge has several applications and we give analyses of two examples that use it. In general, it seems to be the case that applications that involve all processes reaching agreement about some property of a consistent global state are protocols that use concurrent common knowledge.