Showing papers on "Barrier layer published in 1991"

Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact

Abstract: An improved DRAM cell having a tantalum metal lower plate, a tantalum-silicide buried contact, and a tantalum oxide capacitor dielectric layer is disclosed. Also disclosed are several methods for fabricating the improved cell. Fabrication of an array of the improved cells proceeds through the storage-node contact opening stage in a manner consistent with the fabrication process utilized for conventional stacked-cell DRAM arrays. The process for fabricating the improved cells deviates from convention after storage-node contact openings are formed. A tantalum metal layer is conformally deposited over the wafer surface, patterned and etched to create individual storage-node plates. The wafer is then subjected to an elevated temperature step in an oxygen ambient, which creates both a tantalum silicide layer at the tantalum-silicon interface of each storage-node contact, and a tantalum oxide dielectric layer on the exposed surfaces of each storage-node plate. The tantalum oxide layer then annealed in order to reduce its leakage current characteristics. Following the annealing step, a thin barrier layer of a material such as silicon nitride is blanket deposited. This is followed by the deposition of a polysilicon cell plate layer.

Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal nitride barrier layer to block migration of tin through via holes

Abstract: A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16, 18) formed on a frontside surface (12a), and via holes (12c, 12d) formed through the chip (12) from the frontside surface (12a) to a backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c, 12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold-tin alloy (20) through the via holes (12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16, 18).

Forming web for lining a rigid container

Abstract: A forming web suitable for lining the interior of a rigid or semirigid container, such as a box made from corrugated board, includes an outer sealable layer; an interior barrier layer comprising a polymeric material with low oxygen transmission; a polymeric layer which adds bulk to the web; and an inner adherent layer. The web can also include polymeric adhesive layers for bonding the outer sealable layer to the interior layer, and the bulk layer to the interior and inner adherent layers respectively. More than one bulk or barrier layer can be included in the present invention.

Induced junction chalcopyrite solar cell

Abstract: A new solar cell of a I-III-VI 2 semiconductor material that has an inversion layer is provided. The cell comprises a substrate having an electrically conductive, first electrode, a p-conductive, polycrystalline semiconductor layer of chalcopyrite material, a barrier layer composed of an electrically non-conductive material, a second electrode, and an antireflection layer. The anti-reflection layer has stationary, positive charges that induce a negatively charged inversion layer in the boundary surface region of the semiconductor layer relative to the barrier layer. The negatively charged inversion layer serves as an emitter for a space charge zone. In an embodiment the invention comprises a semiconductor layer of copper-indium-diselenide or copper-gallium-diselenide, a barrier layer of silicon dioxide, an anti-reflection layer of silicon nitride, and cesium chloride as the stationary charges.

Plug contact with antifuse

Abstract: An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer, which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer. In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon may be located either below the refractory metal layer or above it. At its bottom, the interconnection layer also has a barrier layer to prevent any intermixing between the amorphous silicon layer and the metal interconnection layer.

Lead-free mirrors and environmentally safe manufacture thereof

Abstract: Mirrors are formed in an environmentally compatible and substantially pollution-free manner by a sputtering process in which a transparent substrate (10) such as glass has first sputtered upon it a primer layer (12) and then a reflective layer (14) of silver or other bright reflective metal. A barrier layer (16) is provided over the reflective layer (14) to protect the latter from corrosive environments. If the transmittance of the reflective layer (14) is greater than zero percent, the barrier layer (16) includes a different bright reflective metal sufficient to reduce the transmittance of the combined reflective and barrier layers to zero percent. The mirror includes a lead-free polymeric protective layer (22) spaced further from the transparent substrate than the barrier layer. The inclusion of zinc pigment in the polymeric coating (26) provides sulfiding protection, and the use of an outer sputtered on film of zinc (24) or zinc oxide (24) provides substantial adhesion thereto of the polymeric coating (26).

High density polyethylene article with oxygen barrier properties

Abstract: An article of manufacture which includes a barrier layer formed of a high density polyethylene composition comprising: from about 50 to about 95 weight percent of high density polyethylene; from about 5 to 40 weight percent of polyisobutylene rubber; and from about 1 to about 30 weight percent of a filler selected from the group consisting of mica, talc and mixtures thereof, the barrier layer having excellent oxygen permeation resistance. The article of manufacture may be a mono- or multi-ply layer, such as a blow-molded bottle.

Method for forming a silicide layer and barrier layer on a semiconductor device rear surface

Abstract: A method of manufacturing a semiconductor device wherein the back surface of a semiconductor chip is adhered closely to a substrate or a seal member through a soldering material or the like, and a metallized layer is formed on the back surface of the chip for attaining good adhesion. The metallized layer according to the present invention is a layer formed by laminating a metal silicide, a barrier metal and an oxidation preventing metal successively on the back of the chip. The layer of the metal silicide can be formed in a known heat treatment process, for example, simultaneously with the formation of bump electrodes, on a main surface of the semiconductor chip by the heat used at the time of forming such bump electrodes, or simultaneously with the mounting of the semiconductor chip by the heat used at the time of the chip mounting.

Flip chip solder bond structure for devices with gold based metallization

Abstract: A flip-chip solder bonding arrangement including a semiconductor substrate having thereon layers of metallization which have a tendency to interact with a solder material, forming on said layers of metallization a barrier metallization layer which is not reactive with said solder material, forming solder pads on the barrier layer and thereafter forming solder bonds with such solder pads employing said solder material.

Membrane Process for Organic Vapor Recovery from Air

Abstract: New organic vapor separation membrane has been developed. Air containing a relatively high organic vapor concentration is fed to the membrane and the organic vapor is selectively extracted. The organic vapor separation membrane is a composite membrane. It consists of a thin skin layer and a porous support layer and nonwoven polyester backing. The skin layer is the selective barrier layer composed of three dimensionally crosslinked elastomeric polymer. Polyimide which has a high resistance to solvents is used for the porous support layer. The composite membrane has an organic vapor permeation rate of 5–20 Nm3/m2hratm, depending on the types of the organic vapors. The permeation rate shows good correlation with the boiling point of the organic vapors. Spiral module type is used for actual application. Vapor concentration after treatment of the module is changed significantly depend on the vapor pressure ratio and flow rate difference between feed side and permeate side of the module.

Process for manufacturing a ferroelectric dynamic/non-volatile memory array using a disposable layer above storage-node junction

Abstract: A process for manufacturing a ferroelectric memory array of stacked-cell design that can be operated in both dynamic and nonvolatile modes. The process deviates from conventional stacked cell array processing at the storage node plate formation stage. A storage node polysilicon layer is conformally deposited, while being in-situ conductively doped, to a depth greater than that necessary to completely fill inter-wordline gaps (if not already planarized) and inter-bitline gaps (in the case of a buried digit line process flow). The storage-node poly layer is then planarized to a level at which poly still covers the entire array. Next, a barrier layer of a refractory metal (e.g., platinum) or of a refractory metal silicide is created on top of the planarized storage-node poly layer. A disposable polyimide layer, which is deposited on top of the barrier layer, is patterned during the same step in which the storage node contact layer and barrier layer are patterned. A silicon dioxide layer is subsequently created via low-temperature chemical vapor deposition. After the this silicon dioxide layer is planarized, thus exposing the polyimide layer remnants, the latter are removed. Next, a PZT dielectric layer is deposited via either the well-known solution-gelatin technique or sputtering. Finally, a refractory metal or refractory metal silicide cell plate layer is deposited. The memory array is completed using standard processing from this point.

Electrophotographic element containing barrier layer

Abstract: A photoconductor element of the type comprising successive layers of a support layer, a barrier layer, a charge generation layer, and an n-type charge transport layer wherein the barrier layer is less than about 1.0 micron in thickness and is comprised of (1) at least one monoethylenically unsaturated aliphatic dicarboxylic acid anhydride containing 4 through 8 carbon atoms per molecule, and (2) at least one vinyl monomer wherein the weight ratio of (1) to (2) is in the range of about 10:1 to 1:10.

Method for field inversion free multiple layer metallurgy VLSI processing

Abstract: A multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.

MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region

Abstract: Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.

Bilayer barrier metal method for obtaining 100% step-coverage in contact vias without junction degradation

Abstract: A process for forming an electrical connection in a semiconductor device between an aluminum interconnect and the substrate avoids junction spiking at temperatures (1000° C.-1500° C.) significantly above the standard semiconductor device fabrication temperatures (<500° C.). An insulating layer is formed over an upper surface of the substrate with a via formed through the insulating layer to expose a portion of the substrate to which electrical connection is to be made. A first refractory metal barrier layer is formed over the insulating layer and the exposed portion of the substrate. Preferably, the first barrier layer is TiN. A second refractory metal barrier layer is formed over the first barrier layer to provide extra thickness and to cap the first barrier layer to minimize the gas emission and enhanced optical ablation due to the first barrier layer during laser planarization, and to provide a wetting layer during and produce a desirable surface morphology after laser planarization. The second layer is preferably Ti. A metal interconnect layer is formed following the deposition of the second barrier layer without breaking vacuum. The metal interconnect layer is preferably aluminum or its alloys. The aluminum layer is annealed above the melting point of the interconnect metal in a very short time to planarize the aluminum and to flow the aluminum to fill any voids. The aluminum and barrier layers are etched to form an appropriate interconnect pattern.

Semiconductor device having a group iii-v epitaxial semiconductor layer on a substrate

Abstract: A semiconductor device comprises a substrate of a first material, a buffer layer of a second, group III-V semiconductor material provided on the substrate epitaxially, and a barrier layer of a third, group III-V compound semiconductor material different from the first and second materials and having a resistivity substantially larger than the resistivity of the buffer layer. The barrier layer further has a second lattice constant different from the lattice constant of the buffer layer and characterized by a band gap substantially larger than the band gap of the buffer layer. The barrier layer is provided on the buffer layer directly and an active layer of a fourth, group III-V compound semiconductor layer is provided on the barrier layer. On the active layer, an active device is provided such that the active device at least has a part formed in the active layer.

Resin composition and heat shrinkable film comprising the same composition layer

Abstract: The present invention discloses a resin composition containing 26˜70 weight % of thermoplastic polyester resin, 10˜30 weight % of polyester elastomer, and 20˜44 weight % of vinylidene chloride resin and a biaxially stretched heat shrinkable film having cold resistance and oxygen gas barrier property comprising said resin composition, and further a biaxially stretched heat shrinkable laminated film having not only oxygen gas barrier property and cold resistance, but also melt hole resistance, heat resistance sealing property, and transparency after the shrinkage and comprising barrier layer of said resin composition, outer layer (polyamide or crosslinkable polyolefin), inner layer (crosslinkable polyolefin), and heat sealable layer (low crosslinkable polyolefin), at least the outer layer, the inner layer and the heat sealing layer being crosslinked by electron beam irradiation.

Oxygen and flavor barrier laminate for liquid packaging

Abstract: A heat-sealable paperboard laminate for liquid packaging which does not transmit nor absorb oxygen or flavor and odor ingredients comprises paperboard sandwiched between two layers of heat-sealable low density polyethylene polymer (LDPE) and including a three-component product-contact barrier layer coextruded onto the inner layer of LDPE. The barrier layer comprises ethylene vinyl alcohol copolymer (EVOH)/a tie layer (Plexar 177 or 175)/ low density polyethylene polymer (LDPE).

Multi-layer film

Abstract: Multi-layered films are disclosed which have a barrier layer and at least one seal layer. The seal layer is made with a copolymer of ethylene and ethylenically unsaturated ester. The seal layer is radio frequency (RF) sealable and the seal layer has an anti-block matted surface. The matted seal layer surface permits a lower slip and anti-block additive level which improves RF sealing and heat sealing.

Filter and solid state imager incorporating this filter

Abstract: A filter is formed on a substrate, such as a solid state imager, by providing successively on the substrate a layer of an absorber material, a layer of a barrier material, and a layer of a photoresist material. The photoresist is patternwise exposed and developed, thereby baring regions of the barrier layer underlying selected regions of the photoresist layer. The coated substrate is reactive ion etched under a first set of etching conditions to etch away the bared regions of the barrier layer and to bare but not substantially etch the underlying regions of the absorber layer, and then reactive ion etched under a second set of etching conditions, thereby etching away the remaining regions of the photoresist layer and the bared regions of the absorber layer, so forming a filter on the substrate. To form multi-colored filters, the process may be repeated with a different dye, or additional dyes may be deposited by other processes, such as that described in U.S. Pat. No. 4,808,501.

Dual laminate process for thermal color proofing

Abstract: A process for forming a color image which may be used to represent a printed color image to be obtained from a printing press comprising (a) forming a thermal dye transfer image in a polymeric dye image-receiving layer of an intermediate dye-receiving element by imagewise-heating a dye-donor element and transferring a dye image to the dye image-receiving layer, (b) applying a dye-migration barrier layer to one surface of a paper substrate, and (c) transferring the imaged polymeric dye image-receiving layer to the surface of the paper having the dye-migration barrier layer applied thereon. By first applying a dye-migration barrier layer to the paper substrate, dye smear and spreading due to migration of dye into the paper can be eliminated and a high quality final color image can be obtained.

Optically switchable device

Abstract: An optically switchable device (1) has a heterostructure (2) defining a first potential well (3) separated by a barrier layer (4) from a second potential well (5) which provides an electron energy level (e5) which is lower in electron energy than the lowest electron energy level (e3) of the first potential well (3). The barrier layer (4) provides an intermediate electron energy level (e4) and is sufficiently thick to inhibit tunnelling of holes from the first (3) to the second (5) potential well. The barrier layer (4) thus confines holes of electron-hole pairs generated in the first potential well (3) by an incident optical beam to the first potential well (3) while facilitating transfer of the electrons from the first potential well (3) to the second potential well (5) via the intermediate electron energy level (e4) provided by the barrier layer (4).

High performance metal x-ray tube target having a reactive barrier layer

Abstract: A high performance x-ray tube rotating target having a reactive barier layer between the substrate and the emissive coating and, if desired, a protective layer of molybdenum between the reactive barrier and the emissive coating is disclosed.

Avalanche photodiode having a thin multilayer superlattice structure sandwiched between barrier and well layers to reduce energy loss

Abstract: An avalanche photodiode includes an avalanche multiplication layer consisting of a superlattice multilayer structure in which a repeated thin multilayer of short-width well layers and short-width barrier layers is sandwiched between a well layer and a barrier layer. The width of the short-width well and barrier layers is preferably up to 100 Å. In such a structure, an ionization rate of electrons in the avalanche multiplication layer increases, so that the avalanche photodiode has low-noise and high speed response performances.

Sputter deposited barrier coatings on SiC monofilaments for use in reactive metallic matrices—III. Microstructural stability in composites based on magnesium and titanium

Abstract: An examination has been made of the chemical stability of SiC monofilaments, with and without sputtered coatings intended to produce diffusion barrier layers of Y2O3, in contact with matrices of Mg Li alloy (up to 400°C) and Ti (up to 1000°C). Even very thin layers were found to offer some protection in the Mg Li alloy, under conditions such that the uncoated fibres suffered catastrophic embrittlement by penetration of Li into the grain boundaries. Yttrium-coated fibres in a Ti matrix were found to exhibit only marginally improved stability when compared with uncoated fibres. The probable explanation for this has been identified as a tendency for Y to penetrate into the SiC fibre before a stable Y2O3 layer could form, although high hydrogen levels in the Ti matrix (absorbed during composite fabrication) may also have impaired the interfacial stability in much of the material examined. Fibre preoxidation prior to Y coating was found to inhibit this Y penetration into the fibre material, allowing a Y2O3 barrier layer to form in situ. This barrier layer has been shown to offer considerable fibre protection.

Barrier laminates for containment of flavor, essential oils and vitamins

Abstract: A laminate providing an effective barrier to migration of essential oils and flavorings and for retention of vitamin C, essential oils and flavor in a juice and cartons made therefrom, wherein the laminate comprises, from the outer surface to the inner surface contacting the juice: an outer polyethylene layer for heat sealing and graphics, a bleached sulfate paperboard substrate, a nylon barrier layer constituting a barrier for oxygen, a first tie layer of modified polyethylene acting as an adherent, another polyethylene layer acting as a heat seal layer and bonded to the nylon barrier layer by the first tie layer, a second tie layer acting as an adherent, and an inner skin layer, which contacts the contents of the carton, which is bonded to the polyethylene layer by the second tie layer, and which may be ethylene vinyl alcohol copolymer (EVOH), polyethylene terephthalate or nylon.

Deodorized multilayer film with vinylidene chloride copolymer barrier

Abstract: In a multilayer thermoplastic film having a vinylidene chloride copolymer barrier and at least a polyolefin second layer laminated to the barrier layer wherein at least the barrier layer is irradiated, hydrotalcite is blended with the polyolefin and substantially reduces odor generation due to ionizing irradiation of the barrier layer.

Insulation and heat reflective barrier

Abstract: A radiant heat barrier layer is sandwiched between and bonded to two closed cell foam layers by non-heat conducting adhesive.

Focal track structures for X-ray anodes and method of preparation thereof

Abstract: An improved high performance x-ray tube having a rotating graphite anode therein and method of preparation thereof. The surface of a graphite anode body is oxidized in air for removing the surface damage caused during the machining of the anode body. The anode body is provided with a diffusion barrier layer of rhenium contiguously disposed on the substantially damage free surface of the anode body. An anode target layer is then deposited on top of the barrier layer.

Optical semiconductor device

Abstract: PURPOSE: To make it possible to deal sufficiently with optical communication technology by setting the band end energy of a first semiconductor layer larger than twice the energy the operation wavelength corresponding to the sub-band intervals of the first semiconductor layer and setting the energy of the operation wavelength corresponding to the sub-band intervals at a specific value or higher. CONSTITUTION: A quantum well structure consisting of a GaN quantum well layer 13 and an AIN first barrier layer 14 is formed on a GaN layer. The band end energy Edge of the GaN well layer 13 is set larger than twice the energy E op of the operation wavelength corresponding to the sub-band intervals of the GaN well layer 13. The band end energy is larger than the energy of two photons if the energy is set in such a manner and, therefore, the probability that the photons are absorbed is extremely low. E op is required to be set at ≥0.75eV which is the band gap of InGaAs to be lattice matched with, for example, InP if the materials and wavelength bands commonly used in optical communication are taken into consideration. COPYRIGHT: (C)1996,JPO