Showing papers on "Binary number published in 2010"

BRIEF: binary robust independent elementary features

Abstract: We propose to use binary strings as an efficient feature point descriptor, which we call BRIEF. We show that it is highly discriminative even when using relatively few bits and can be computed using simple intensity difference tests. Furthermore, the descriptor similarity can be evaluated using the Hamming distance, which is very efficient to compute, instead of the L2 norm as is usually done. As a result, BRIEF is very fast both to build and to match. We compare it against SURF and U-SURF on standard benchmarks and show that it yields a similar or better recognition performance, while running in a fraction of the time required by either.

$${{{\mathbb Z}_2}{{\mathbb Z}_4}}$$ -linear codes: generator matrices and duality

Abstract: A code $${{\mathcal C}}$$ is $${{{\mathbb Z}_2}{{\mathbb Z}_4}}$$ -additive if the set of coordinates can be partitioned into two subsets X and Y such that the punctured code of $${{\mathcal C}}$$ by deleting the coordinates outside X (respectively, Y) is a binary linear code (respectively, a quaternary linear code). In this paper $${{{\mathbb Z}_2}{{\mathbb Z}_4}}$$ -additive codes are studied. Their corresponding binary images, via the Gray map, are $${{{\mathbb Z}_2}{{\mathbb Z}_4}}$$ -linear codes, which seem to be a very distinguished class of binary group codes. As for binary and quaternary linear codes, for these codes the fundamental parameters are found and standard forms for generator and parity-check matrices are given. In order to do this, the appropriate concept of duality for $${{{\mathbb Z}_2}{{\mathbb Z}_4}}$$ -additive codes is defined and the parameters of their dual codes are computed.

Improved Design of High-Performance Parallel Decimal Multipliers

Abstract: The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2n-tuples (and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix--8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication.

Automatic Parallelization in a Binary Rewriter

Abstract: Today, nearly all general-purpose computers are parallel, but nearly all software running on them is serial. However bridging this disconnect by manually rewriting source code in parallel is prohibitively expensive. Automatic parallelization technology is therefore an attractive alternative. We present a method to perform automatic parallelization in a binary rewriter. The input to the binary rewriter is the serial binary executable program and the output is a parallel binary executable. The advantages of parallelization in a binary rewriter versus a compiler include (i) compatibility with all compilers and languages, (ii) high economic feasibility from avoiding repeated compiler implementation, (iii) applicability to legacy binaries, and (iv) applicability to assembly-language programs. Adapting existing parallelizing compiler methods that work on source code to work on binary programs instead is a significant challenge. This is primarily because symbolic and array index information used in existing compiler parallelizers is not available in a binary. We show how to adapt existing parallelization methods to achieve equivalent parallelization from a binary without such information. Preliminary results using our x86 binary rewriter called Second Write on a suite of dense-matrix regular programs including the externally developed Polybench suite of benchmarks shows an average speedup of 5.1 from binary and 5.7 from source with 8 threads compared to the input serial binary on an x86 Xeon E5530 machine, and 14.7 from binary and 15.4 from source with 32 threads compared to the input serial binary on a SPARC T2. Such regular loops are an important component of scientific and multi-media workloads, and are even present to a limited extent in otherwise non-regular programs.

A framework to express variant and invariant functional spaces for binary logic

Abstract: A new framework has been developed to express variant and invariant properties of functions operating on a binary vector space. This framework allows for manipulation of dynamic logic using basic operations and permutations. Novel representations of binary functional spaces are presented. Current ideas of binary functional spaces are extended and additional conditions are added to describe new function representation schemes: F code and C code. Sizes of the proposed functional space representation schemes were determined. It was found that the complete representation for any set of functions operating on a binary sequence of numbers is larger than previously thought. The complete representation can only be described using a structure having a space of size % MathType!MTEF!2!1!+- % feaagaart1ev2aaatCvAUfKttLearuqr1ngBPrgarmWu51MyVXgatC % vAUfeBSjuyZL2yd9gzLbvyNv2CaeHbd9wDYLwzYbItLDharyavP1wz % ZbItLDhis9wBH5garqqr1ngBPrgifHhDYfgasaacH8srps0lbbf9q8 % WrFfeuY-Hhbbf9v8qqaqFr0xc9pk0xbba9q8WqFfea0-yr0RYxir-J % bba9q8aq0-yq-He9q8qqQ8frFve9Fve9Ff0dmeaabaqaciGacaGaae % qabaWaaqaafaaakeaaiqaacaWFYaWaaWbaaSqabeaacaWFYaWaaWba % aWqabeaaiqGacaGFUbaaaaaakiabgEna0kaa-jdadaahaaWcbeqaai % aa+5gaaaGccqGGHaqiaaa!440C! $$ 2^{2^n } \times 2^n ! $$ for any given space of functions acting on a binary sequence of length n. The framework, along with the proposed coding schemes provides a foundational theory of variant and invariant logic in software and electric-electronic technology and engineering, and has uses in the analysis of the stability of rule-based, dynamic binary systems such as cellular automata.

An efficient bit reduction binary multiplication algorithm using vedic methods

Abstract: An efficient technique for multiplying two binary numbers using limited power and time is presented in this paper. The work mainly focuses on speed of the multiplication operation of multipliers, by reducing the number of bits to be multiplied. The framework of the proposed algorithm is taken from Mathematical algorithms given in Vedas and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting. The proposed algorithm was modeled using Verilog, a hardware description language. It was found that under a given 3.3 V supply voltage, the designed 4 bit multiplier dissipates a power of 47.35 mW. The propagation time of the proposed architecture was found to 6.63ns

Efficient software implementation of binary field arithmetic using vector instruction sets

Abstract: In this paper we describe an efficient software implementation of characteristic 2 fields making extensive use of vector instruction sets commonly found in desktop processors. Field elements are represented in a split form so performance-critical field operations can be formulated in terms of simple operations over 4-bit sets. In particular, we detail techniques for implementing field multiplication, squaring, square root extraction and present a constant-memory lookup-based multiplication strategy. Our representation makes extensive use of the parallel table lookup (PTLU) instruction recently introduced in popular desktop platforms and follows the trend of accelerating implementations of cryptography through PTLU-style instructions. We present timings for several binary fields commonly employed for curve-based cryptography and illustrate the presented techniques with executions of the ECDH and ECDSA protocols over binary curves at the 128-bit and 256-bit security levels standardized by NIST. Our implementation results are compared with publicly available benchmarking data.

Modified Padovan words and the maximum number of runs in a word

Abstract: A run (or maximal periodicity) in a word is a periodic factor whose length is at least twice the period and which cannot be extended to the left or right without changing the period. Recently Kusano et al. [6] used a clever search technique to find run-rich words and were able to show that the number of runs in a word of length n can be greater than 0.94457564n. In this paper we use a two-stage process to construct words with a (very slightly) higher run density than theirs. We first produce ternary words which we call Modified Padovan words, then apply a morphism to these to produce run-rich binary words. The Modified Padovan words have interesting and surprising properties.

Binary Representations of Fingerprint Spectral Minutiae Features

Abstract: A fixed-length binary representation of a fingerprint has the advantages of a fast operation and a small template storage. For many biometric template protection schemes, a binary string is also required as input. The spectral minutiae representation is a method to represent a minutiae set as a fixed-length real-valued feature vector. In order to be able to apply the spectral minutiae representation with a template protection scheme, we introduce two novel methods to quantize the spectral minutiae features into binary strings: Spectral Bits and Phase Bits. The experiments on the FVC2002 database show that the binary representations can even outperformed the spectral minutiae real-valued features.

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Abstract: This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub-binary radix M/2+M DAC, which has the advantage of allowing reaching arbitrarily high resolutions at the cost of extremely small area. The methodology proposed allows the removal of any type of imperfections, at the expense of two shift registers, a few logical gates and a DAC which is smaller than the shift register.

Fiber-Based Programmable Picosecond Optical Pulse Shaper

Abstract: We experimentally demonstrate a fiber-optic programmable optical pulse shaper based on time-domain binary phase-only linear filtering, which is capable of switching picosecond pulse shapes at unprecedented sub-GHz rates by simply updating the binary signal driving an electro-optic phase-modulator (EO-PM). The required binary phase-filtering functions are computed using a genetic algorithm (GA). One limitation of the binary phase-filtering approach is the inherent symmetry of the output temporal shapes. To generate fully arbitrary time-domain intensity profiles (including asymmetric temporal waveforms) we must employ a multi-level phase-filtering function. However, the size of the solution-space and complexity of the computation multiplies to manifolds as the number of levels in the phase-filtering function increases. Here we numerically demonstrate a simple strategy, by combining the Gerchberg-Saxton algorithm (GSA) and GA, for the fast computation of multi-level phase-filtering functions. The performance of this approach is numerically proven by generating different asymmetric pulse shapes of practical interest, assuming experimentally feasible design parameters.

An Approximation Approach for Representing S-Shaped Membership Functions

Abstract: In general, to formulate a fuzzy-linear-programming problem with n S-shaped utility (membership) functions, traditional methods require n or more extra binary variables because S-shaped curves are neither convex nor concave in all places. Adding binary variables does not improve the bound of the linear-programming relaxation. On the contrary, added binary variables increase the computational burden in the solution process if problems get large. Therefore, a formulation without binary variables should be more efficient. Accordingly, this study proposes a piecewise-linear approach to formulate an S-shaped membership function (MF) without adding any extra binary variables, which improves the efficiency of fuzzy-linear programming in solving decision/management problems with S-shaped MFs. Finally, a computational experiment is provided to demonstrate the superiority of the proposed models. An illustrative example is also provided to show the usefulness of the proposed method.

A high performance binary TO BCD converter for decimal multiplication

Abstract: Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. Binary to BCD conversion forms the basic building block of decimal digit multipliers. This paper presents novel high speed low power architecture for fixed bit binary to BCD conversion which is at least 28% better in terms of power-delay product than the existing designs.

Surface extraction from binary volumes with higher-order smoothness

Abstract: A number of 3D shape reconstruction algorithms, in particular 3D image segmentation methods, produce their results in the form of binary volumes, where a binary value indicates whether a voxel is associated with the interior or the exterior. For visualization purpose, it is often desirable to convert a binary volume into a surface representation. Straightforward extraction of the median isosurfaces for binary volumes using the marching cubes algorithm, however, produces jaggy, visually unrealistic meshes. Therefore, similarly to some previous works, we suggest to precede the isosurface extraction by replacing the original binary volume with a new continuous-valued embedding function, so that the zero-isosurface of the embedding function is smooth but at the same time consistent with the original binary volume. In contrast to previous work, computing such an embedding function in our case permits imposing a higher-order smoothness on the embedding function and involves solving a convex optimization problem. We demonstrate that the resulting separating surfaces are smoother and of better visual quality than minimal area separating surfaces extracted by previous approaches to the problem. The code of the algorithm is publicly available.

High-efficiency self-adjusting switched capacitor dc-dc converter with binary resolution

Abstract: Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.

Implementation of binary edwards curves for very-constrained devices

Abstract: Elliptic Curve Cryptography (ECC) is considered as the best candidate for Public-Key Cryptosystems (PKC) for ubiquitous security. Recently, Elliptic Curve Cryptography (ECC) based on Binary Edwards Curves (BEC) has been proposed and it shows several interesting properties, e.g., completeness and security against certain exceptional-points attacks. In this paper, we propose a hardware implementation of the BEC for extremely constrained devices. The w-coordinates and Montgomery powering ladder are used. Next, we also give techniques to reduce the register file size, which is the largest component of the embedded core. Thirdly, we apply gated clocking to reduce the overall power consumption. The implementation has a size of 13,427 Gate Equivalent (GE), and 149.5 ms are required for one point multiplication. To the best of our knowledge, this is the first hardware implementation of binary Edwards curves.

A Novel Speaker Binary Key Derived from Anchor Models

Abstract: The approach presented in this paper represents voice recordings by a novel acoustic key composed only of binary values. Except for the process being used to extract such keys, there is no need for acoustic modeling and processing in the approach proposed, as all the other elements in the system are based on the binary vectors. We show that this binary key is able to effectively model a speaker’s voice and to distinguish it from other speakers. Its main properties are its small size compared to current speaker modeling techniques and its low computational cost when comparing different speakers as it is limited to obtaining a similarity metric between two binary vectors. Furthermore, the binary key vector extraction process does not need any threshold and offers the opportunity to set the decision steps in a well defined binary domain where scores and decisions are easy to interpret and implement. Index Terms: binary key, speaker modeling, biometrics

‘Disc–Jet’ Coupling in Black Hole X-Ray Binaries and Active Galactic Nuclei

Abstract: In this chapter I will review the status of our phenomenological understanding of the relation between accretion and outflows in accreting black hole systems. This understanding arises primarily from observing the relation between X-ray and longer wavelength (infrared, radio) emission. The view is necessarily a biased one, beginning with observations of X-ray binary systems, and attempting to see if they match with the general observational properties of active galactic nuclei.

Co-Z Addition Formulæ and Binary Ladders on Elliptic Curves

Abstract: Meloni recently introduced a new type of arithmetic on elliptic curves when adding projective points sharing the same Z-coordinate This paper presents further co-Z addition formulae (and register allocations) for various point additions on Weierstras elliptic curves It explains how the use of conjugate point addition and other implementation tricks allow one to develop efficient scalar multiplication algorithms making use of co-Z arithmetic Specifically, this paper describes efficient co-Z based versions of Montgomery ladder and Joye’s double-add algorithm Further, the resulting implementations are protected against a large variety of implementation attacks

Instantaneous noise-based logic

Abstract: We show two universal, Boolean, deterministic logic schemes based on binary noise timefunctions that can be realized without time-averaging units. The first scheme is based on a new bipolar random telegraph wave scheme and the second one makes use of the recent noise-based logic which is conjectured to be the brain's method of logic operations [Phys. Lett. A 373 (2009) 2338–2342]. Error propagation and error removal issues are also addressed.

Efficient Sketches for the Set Query Problem

Abstract: We develop an algorithm for estimating the values of a vector x in R^n over a support S of size k from a randomized sparse binary linear sketch Ax of size O(k). Given Ax and S, we can recover x' with ||x' - x_S||_2 <= eps ||x - x_S||_2 with probability at least 1 - k^{-\Omega(1)}. The recovery takes O(k) time. While interesting in its own right, this primitive also has a number of applications. For example, we can: 1. Improve the linear k-sparse recovery of heavy hitters in Zipfian distributions with O(k log n) space from a (1+eps) approximation to a (1 + o(1)) approximation, giving the first such approximation in O(k log n) space when k <= O(n^{1-eps}). 2. Recover block-sparse vectors with O(k) space and a (1+eps) approximation. Previous algorithms required either omega(k) space or omega(1) approximation.

Co-Z Addition Formulæ and Binary Ladders on

Abstract: Meloni recently introduced a new type of arithmetic on elliptic curves when adding projective points sharing the same Z-coordinate. This paper presents further co-Z addition formulae for various point additions on Weierstras elliptic curves. It explains how the use of conjugate point addition and other implementa- tion tricks allow one to develop efficient scalar multiplication algorithms making use of co-Z arithmetic. Specifically, this paper describes efficient co-Z based versions of Montgomery ladder and Joye's double-add algorithm. Further, the re- sulting implementations are protected against a large variety of implementation attacks.

The Linear Complexity of Binary Sequences With Optimal Autocorrelation

Abstract: Binary sequences with optimal autocorrelation are needed in many applications. Two constructions of binary sequences with optimal autocorrelation of period N ≡ 0 (mod 4) are investigated. The two constructions are powerful and generic in the sense that many classes of binary sequences with optimal autocorrelation could be obtained from binary sequences with ideal autocorrelation. General results on the minimal polynomials of these binary sequences are derived. Based on the results, both the linear complexities and the minimal polynomials are determined.