Showing papers on "Block (data storage) published in 2008"

Scalable and efficient provable data possession

Abstract: Storage outsourcing is a rising trend which prompts a number of interesting security issues, many of which have been extensively investigated in the past. However, Provable Data Possession (PDP) is a topic that has only recently appeared in the research literature. The main issue is how to frequently, efficiently and securely verify that a storage server is faithfully storing its client's (potentially very large) outsourced data. The storage server is assumed to be untrusted in terms of both security and reliability. (In other words, it might maliciously or accidentally erase hosted data; it might also relegate it to slow or off-line storage.) The problem is exacerbated by the client being a small computing device with limited resources. Prior work has addressed this problem using either public key cryptography or requiring the client to outsource its data in encrypted form.In this paper, we construct a highly efficient and provably secure PDP technique based entirely on symmetric key cryptography, while not requiring any bulk encryption. Also, in contrast with its predecessors, our PDP technique allows outsourcing of dynamic data, i.e, it efficiently supports operations, such as block modification, deletion and append.

The DiskSim Simulation Environment Version 4.0 Reference Manual (CMU-PDL-08-101)

Abstract: DiskSim is an efficient, accurate and highly-configurable disk system simulator developed to support research into various aspects of storage subsystem architecture. It includes modules that simulate disks, intermediate controllers, buses, device drivers, request schedulers, disk block caches, and disk array data organizations. In particular, the disk drive module simulates modern disk drives in great detail and has been carefully validated against several production disks (with accuracy that exceeds any previously reported simulator). It also includes a MEMS-based storage device module. This manual describes how to configure and use DiskSim, which has been made publicly available with the hope of advancing the state-of-the-art in disk system performance evaluation in the research community. The manual also briefly describes DiskSim’s internal structure and various validation results.

BPLRU: a buffer management scheme for improving random writes in flash storage

Abstract: Flash memory has become the most important storage media in mobile devices, and is beginning to replace hard disks in desktop systems However, its relatively poor random write performance may cause problems in the desktop environment, which has much more complicated requirements than mobile devices While a RAM buffer has been quite successful in hard disks to mask the low efficiency of random writes, managing such a buffer to fully exploit the characteristics of flash storage has still not been resolved In this paper, we propose a new write buffer management scheme called Block Padding Least Recently Used, which significantly improves the random write performance of flash storage We evaluate the scheme using trace-driven simulations and experiments with a prototype implementation It shows about 44% enhanced performance for the workload of MS Office 2003 installation

The DiskSim Simulation Environment Version 4.0 Reference Manual

Abstract: DiskSim is an efficient, accurate and highly-configurable disk system simulator developed to support research into various aspects of storage subsystem architecture. It includes modules that simulate disks, intermediate controllers, buses, device drivers, request schedulers, disk block caches, and disk array data organizations. In particular, the disk drive module simulates modern disk drives in great detail and has been carefully validated against several production disks (with accuracy that exceeds any previously reported simulator). It also includes a MEMS-based storage device module. This manual describes how to configure and use DiskSim, which has been made publicly available with the hope of advancing the state-of-the-art in disk system performance evaluation in the research community. The manual also briefly describes DiskSim’s internal structure and various validation results.

Method and system for storage of data in non-volatile media

Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Partial block erase architecture for flash memory

Abstract: A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.

A method and an apparatus for processing a video signal

Abstract: An apparatus for processing a video signal and method thereof are disclosed. The present invention includes receiving prediction mode information, interpolating information and a residual of a current block, reconstructing an interpolating pixel using the interpolating information and a neighbor block, and reconstructing the current block using the interpolating pixel, the prediction mode information and the residual, wherein the interpolating information is generated based on a location of the current block. According to an apparatus and method for processing a video signal, high reconstruction rate can be obtained by improving the related art method having limited intra prediction modes available for a current block located on a boundary area of a picture in encoding in a manner of reconstructing and using an interpolating pixel based on interpolating information.

Access control to block storage devices for a shared disk based file system

Abstract: For enhanced access control, a client includes a token in each read or write command sent to a block storage device. The block storage device evaluates the token to determine whether or not read or write access is permitted at a specified logical block address. For example, the token is included in the logical block address field of a SCSI read or write command. The client may compute the token as a function of the logical block address of a data block to be accessed, or a metadata server may include the token in each block address of each extent reported to the client in response to a metadata request. For enhanced security, the token also is a function of a client identifier, a logical unit number, and access rights of the client to a particular extent of file system data blocks.

Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices

Abstract: A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

Dynamic Time-Spectrum Block Allocation For Cognitive Radio Networks

Abstract: Dynamic time-spectrum block allocation for cognitive radio networks is described. In one implementation, without need for a central controller, peer wireless nodes collaboratively sense local utilization of a communication spectrum and collaboratively share white spaces for communication links between the nodes. Sharing local views of the spectrum utilization with each other allows the nodes to dynamically allocate non-overlapping time-frequency blocks to the communication links between the nodes for efficiently utilizing the white spaces. The blocks are sized to optimally pack the available white spaces. The nodes regularly readjust the bandwidth and other parameters of all reserved blocks in response to demand, so that packing of the blocks in available white spaces maintains a fair distribution of the overall bandwidth of the white spaces among active communication links, minimizes finishing time of all communications, reduces contention overhead among the nodes contending for the white spaces, and maintains non-overlapping blocks.

System and method for organizing data to facilitate data deduplication

Abstract: A technique for organizing data to facilitate data deduplication includes dividing a block-based set of data into multiple “chunks”, where the chunk boundaries are independent of the block boundaries (due to the hashing algorithm). Metadata of the data set, such as block pointers for locating the data, are stored in a tree structure that includes multiple levels, each of which includes at least one node. The lowest level of the tree includes multiple nodes that each contain chunk metadata relating to the chunks of the data set. In each node of the lowest level of the buffer tree, the chunk metadata contained therein identifies at least one of the chunks. The chunks (user-level data) are stored in one or more system files that are separate from the buffer tree and not visible to the user.

Emerging bad block detection

Abstract: Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices (106), such as NAND flash. For example, disclosed techniques can be embodied in a device driver (110) of an operating system (104). Errors are tracked during read operations. If sufficient errors are observed (204) during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written (210), (212), (214), (310). One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed (410) to a more reliable read mode to attempt to recover data. One embodiment further returns data (106) from the memory device regardless of whether the data was correctable (430) by decoding of error correction code data or not.

Wear leveling method and controller using the same

Abstract: A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.

Method and Apparatus for Block-Based Compression of Light-field Images

Abstract: A method and apparatus for the block-based compression of light-field images. Light-field images may be preprocessed by a preprocessing module into a format that is compatible with the blocking scheme of a block-based compression technique, for example JPEG. The compression technique is then used to compress the preprocessed light-field images. The light-field preprocessing module reshapes the angular data in a captured light-field image into shapes compatible with the blocking scheme of the compression technique so that blocking artifacts of block-based compression are not introduced in the final compressed image. Embodiments may produce compressed 2D images for which no specific light-field image viewer is needed to preview the full light-field image. Full light-field information is contained in one compressed 2D image.

Scalable and Efficient Provable Data Possession.

Abstract: Storage outsourcing is a rising trend which prompts a number of interesting security issues, many of which have been extensively investigated in the past. However, Provable Data Possession (PDP) is a topic that has only recently appeared in the research literature. The main issue is how to frequently, efficiently and securely verify that a storage server is faithfully storing its client’s (potentially very large) outsourced data. The storage server is assumed to be untrusted in terms of both security and reliability. (In other words, it might maliciously or accidentally erase hosted data; it might also relegate it to slow or off-line storage.) The problem is exacerbated by the client being a small computing device with limited resources. Prior work has addressed this problem using either public key cryptography or requiring the client to outsource its data in encrypted form. In this paper, we construct a highly efficient and provably secure PDP technique based entirely on symmetric key cryptography, while not requiring any bulk encryption. Also, in contrast with its predecessors, our PDP technique allows outsourcing of dynamic data, i.e, it efficiently supports operations, such as block modification, deletion and append.

Nonvolatile semiconductor memory device

Abstract: The disclosed invention provides a technique for efficiently avoiding read disturbance. A nonvolatile semiconductor memory device includes a nonvolatile memory unit and a controller that can control refresh processing for rewriting data in a block of blocks assumed to be erasable units in the nonvolatile memory unit into anther block different from the block. The controller sets up a first area and a second area different from the first area in the nonvolatile memory unit and, each time a refresh trigger occurs, executes refresh processing for the first area and the second area, such that a refresh frequency of data in the first area will become higher than a refresh frequency of data in the second area. Thereby, it is possible to efficiently avoid read disturbance when read access is repeated.

Method For Page- And Block Based Scrambling In Non-Volatile Memory

Abstract: A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random number which is generated based on a page of the memory device to which the data is to be written, to provide first scrambled data, which is scrambled using a second pseudo random number which is generated based on a block of the memory device to which the data is to be written. This avoids bit line-to-bit line and block-to-block redundancies which can result in read errors. The data may also be scrambled using a third pseudo random number that depends on a section within a page. Scrambling may also be based on one or more previous pages which were written.

Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories

Abstract: Several parallel architectures such as GPUs and the Cell processor have fast explicitly managed on-chip memories, in addition to slow off-chip memory. They also have very high computational power with multiple levels of parallelism. A significant challenge in programming these architectures is to effectively exploit the parallelism available in the architecture and manage the fast memories to maximize performance.In this paper we develop an approach to effective automatic data management for on-chip memories, including creation of buffers in on-chip (local) memories for holding portions of data accessed in a computational block, automatic determination of array access functions of local buffer references, and generation of code that moves data between slow off-chip memory and fast local memories. We also address the problem of mapping computation in regular programs to multi-level parallel architectures using a multi-level tiling approach, and study the impact of on-chip memory availability on the selection of tile sizes at various levels. Experimental results on a GPU demonstrate the effectiveness of the proposed approach.

Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear

Abstract: A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.

Direct access storage system with combined block interface and file interface access

Abstract: A storage system includes a storage controller and storage media for reading data from or writing data to the storage media in response to block-level and file-level I/O requests. The storage controller includes suitable interfaces for receiving the read/write requests and effecting the reading of data to or the writing of data to the storage media.

Method for Operating a Fixed Prefix Peer to Peer Network

Abstract: A fixed prefix peer to peer network has a number of physical nodes. The nodes are logically divided into a number of storage slots. Blocks of data are erasure coded into original and redundant data fragments and the resultant fragments of data are stored in slots on separate physical nodes such that no physical node has more than one original and/or redundant fragment. The storage locations of all of the fragments are organized into a logical virtual node (e.g., a supernode). Thus, the supernode and the original block of data can be recovered even if some of the physical nodes are lost.

Dynamic SLC/MLC blocks allocations for non-volatile memory

Abstract: Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.

An extended block arnoldi algorithm for large-scale solutions of the continuous-time algebraic riccati equati on ∗

Abstract: We present a new iterative method for the computation of approximate solutions to large-scale continuous-time algebraic Riccati equations. The proposed method is a projection method onto an extended block Krylov subspace, which can be seen as a sum of two block Krylov subspaces in A and A 1 . We give some the- oretical results and present numerical experiments for large and sparse problems. These numerical tests show the efficiency of the proposed scheme as compared to the block Arn oldi and Newton-ADI methods.

Method and apparatus for block level data de-duplication

Abstract: Techniques for performing de-duplication for data blocks in a computer storage environment. At least one chunking/hashing unit receives input data from a source and processes it to output data blocks and content addresses for them. In one aspect, the chunking/hashing unit outputs all blocks without checking to see whether any is a duplicate of a block previously stored on the storage environment. In another aspect, each data block is processed by one of a plurality of distributed object addressable storage (OAS) devices that each is selected to process data blocks having content addresses with a particular range. The OAS devices determine whether each received data block is a duplicate of another previously stored on the computer storage environment, and when it is not, stores the data block.

Runtime FPGA Partial Reconfiguration

Abstract: Field-programmable gate arrays (FPGAs) are now being integrated into many space-based applications. FPGAs are being used as replacements for application-specific integrated circuits (ASICs) without considering new options offered by their reprogrammable nature. Runtime partial reconfiguration can potentially reduce the number of devices or the device size, thereby reducing both size and power consumption. A system that requires either transmit or receive capabilities at any given time, but not both, can switch between the two modes in a fraction of a second using partial reconfiguration. The current approach requires that both modes be implemented simultaneously, thereby wasting power and requiring more resources. The idea of adaptively allocating limited FPGA resources is also applicable to hardware-accelerated software-defined radios. The hardware accelerators are loaded into FPGA(s) as they are needed. Partial reconfiguration allows swapping of accelerators much faster than is possible with current methods, and with less disruption to other processes running in parallel. This technology significantly reduces power consumption critical for space and portable ground-based applications of FPGA technology. A software-defined radio was designed with a reprogrammable forward error correction (FEC) block supporting multiple FEC codes to demonstrate one practical use of this technology. This paper provides an overview of the design flow necessary for partial reconfiguration and comments on the additional overhead necessary for creating such a design. In addition, limitations to this emerging technology are outlined.