Showing papers on "Circuit switching published in 1987"

A Broadband Packet Switch for Integrated Transport

Abstract: This paper gives a broadband (total throughput approaching 1 terabit/s) self-routing packet switch design for providing flexible multiple bit-rate broadband services for an end-to-end fiber network. The switch fabric for the slotted broadband packet switch delivers exactly one packet to each output port from one of the input ports which request packet delivery to that output port. The denied requests would try again during the next slot. We discover an effective scheme, implemented by CMOS VLSI with manageable complexity, for performing this function. First, each input port sends a request for a port destination through a Batcher Sorting network, which sorts the request destinations in ascending order so that we may easily purge all but one request for the same destination. The winning request acknowledges its originating port from the output of the Batcher network, with the acknowledgment routed through a Batcher-banyan selfrouting switch. The acknowledged input port then sends the full packet through the same Batcher-banyan switch without any conflict. Unacknowledged ports buffer the blocked packet for reentry in the next cycle. We also give several variations for significantly improved performance. We then study switch performance based on some rudimentary protocols for traffic control. For the basic scheme, we analyze the throughput-delay characteristics for random traffic, modeled by random output port requests and a binomial distribution of packet arrival. We demonstrate with a buffer size of around 20 packets, we can achieve a 50 percent loading with almost no buffer overflow. Maximum throughput of switch is 58 percent. Next, we investigate the performance of the switch in the presence of periodic broadband traffic. We then apply circuit switching techniques and packet priority for high bit-rate services in our packet switch environment. We improve the throughput per port to close to 100 percent by means of parallel switch fabric, while maintaining the periodic nature of the traffic.

Packet switching system arranged for congestion control through bandwidth management

Abstract: In a packet switching network, packet monitoring and marking algorithms are used for determining which data packets, received from a customer by an access node, are being transmitted at an excessive transmission rate and accordingly are marked. Additionally every packet from a special customer can be marked. Along in the network, marked packets are dropped where the network is congested along the path being traversed by the data packets.

Slotted Random Access Spread-Spectrum Networks: An Analytical Framework

Abstract: An analytic framework is proposed for the study of singlehop spread-spectrum networks using random access and packet switching under various network topologies and channel conditions. The key feature of the theory is the identification of a set of probabilistic parameters, which, based on a symmetry argument, serve to efficiently summarize the effect on performance of various network considerations such as transmitter-receiver configuration, spreadspectrum code allocation, error correction and detection mechanisms, spreading format, jamming conditions, etc. Examples investigating capture effects, coding tradeoffs, and scheduling optimizations are presented. Various previously known results are shown to be special cases of the framework that we describe.

Method and apparatus for eliminating unsuccessful tries in a search tree

Abstract: A circuit switching system in an M-ary, n-cube connected network completes a best-first path from an originating node to a destination node by latching valid legs of the path as the path is being sought out. Each network node is provided with a routing hyperswitch sub-network, ("HSN") connected between that node and bidirectional high capacity communication channels of the n-cube network. The sub-networks are all controlled by routing algorithms which respond to message identification headings ("headers") on messages to be routed along one or more routing legs. The header includes information embedded therein which is interpreted by each sub-network to route and historically update the header. A logic circuit, available at every node, implements the algorithm and automatically forwards or back-tracks the header in the network legs of various paths until a completed path is latched.

N-stage planar optical permutation network

Abstract: This paper describes the construction of a permutation network which is advantageous for optical switching. The switching architecture is planar and does not require optical path crossovers between crosspoints. The network can be partitioned if necessary to ease fabrication difficulties. An algorithm is given to set the binary cells in the network to achieve any specified permutation, and it is shown that no planar N × N network can achieve such rearrangeability with fewer than the N(N − 1)/2 crosspoints used here.

Broadband ISDN Switching Capabilities from a Services Perspective

Abstract: Broadband switching and transmission technologies are maturing rapidly, promising to make broadband ISDN (B-ISDN) possible and potentially economical in the near future. The diversity of possible B-ISDN services provides much impetus for the implementation of B-ISDN, but complicates the task of specifying network switching requirements. This paper examines a few representative services in order to generate a set of basis vectors in capability space. New services are then projected onto this basis; if a new service cannot be constructed from the basis vectors, other vectors are added to the basis set. B-ISDN architects can then specify switching requirements by selecting those capability basis vectors that are required for the services most in demand. For full motion entertainment video services, circuit switching capability at about 150 Mbit/s may be required, while selective broadcast and remote switching capabilities may reduce the cost of these services. For subvideo-rate services, new transfer mode (NTM) capability may be required to allow users the flexibility to allocate access channels dynamically on a per-call basis. Multiple connection (e.g., voice and video) and multiple party call capabilities may be required for many B-ISDN services, implying a need to extend the ISDN signaling protocol. The capability for the user to request network code conversion between different coding formats (e.g., NTSC or HDTV), and network compression of signals to reduce the cost of interoffice facilities, may also be required. Finally, fast call setup capability and high calling volume capabilities may be required, implying a need to distribute call processing functions over multiple processors in the central office.

High-speed modular switching apparatus for circuit and packet switched traffic

Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i) The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port The switch fabric consists of parallel equal switching slices, eg binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports

Photonic switch with optically self-routed bit switching

Abstract: hotonic switches capable of routing wideband optical signals will be an important element of ultrahigh-capacity fiber-optic networks of the future [ 1,2]. A photonic switch generally consists of a multistage connecting network-each stage comprising switching devices and controllers-which routes optical information between input and output ports. We restrict our attention here to photonic switching devices which maintain signals in optical form as they traverse the switch. The controllers process address information supplied by the source. This processing can be performed either electronically or optically. The controller output sets u p the appropriate switch permutation to route the signal to its destination. This control signal may be either electrical or optical, depending upon whether switching is accomplished by an electro-optic or opto-optic effect. Photonic switching devices which have been previously demonstrated include 2x2 integrated-optic wave-guide switches, controlled electrically [3-51. Arrays of these 2x2 switching devices have been organized in NXN crossbar configurations [6-91. Crossbar switch arrays can be further cascaded into photonic switching networks [ 101. Recently, optically-controlled photonic switching devices have also been developed [11,12] and are expected to ultimately switch at speeds in excess of 1 THz [ 131. Whatever photonic switching device is used, the speed of future photonic switches will be limited not only by the device switching speed, but by the speed of the controller. A severe data flow bottleneck will occur at the controller if electronic processing is used. This bottleneck can be eliminated with optical processing. In switches requiring electro-optic control, the output of the optical processor must be converted to an electrical signal to activate the switch. In future photonic switches employing opto-optic control, this conversion would not be necessary. T h e speed of such a switch would then be limited by the speed of the optical decision-making process or the speed of the photonic switching device itself. There have been few proposals of photonic switches with optically-processed control. Haque and Arozullah [14] have proposed that some of the electronic functions in a conventional electronic switch be replaced by their optical or electro-optic counterparts. We propose to improve the performance of photonic switches by developing a novel optical architecture with optically-processed control which could not be implemented with electronic components. Distinguishing characteristics of optical processing include its inherent parallelism and non-interfering nature as well as its high speed [ 151. We report the experimental demonstration of a photonic switch using optically self-routed …

Performance of a Service Independent Switching Network with Distributed Control

Abstract: This paper describes a switching network which is service independent and able to transport services of any bit rate, based on the fast packet switching concept. The control of the switching network is completely distributed; the path select is not centrally controlled, but gradually performed as the control packet is passing through the switching network. The switching network is a multistage network constructed with independent switching elements. The self-routing principle is applied. The load control of the different links between the switching elements in the network is provided by a static load control mechanism, applied to the logical connections granted on these links. Logical connections are accepted or rejected according to the already present load on each link. Possible overload caused by bursty traffic is solved by buffers within the switching elements. Simulation results are discussed, both for the static and dynamic behavior of the exchange. For both simulations, a large mix of different services is evaluated and conclusions are described.

The Performance of Random and Optimal Scheduling in a Time-Multiplex Switch

Abstract: In a time-multiplex switching system, the incoming traffic must be scheduled to avoid conflict at the switch output (two or more users converging simultaneously upon a single output). Two scheduling algorithms, random scheduling and optimal scheduling, are explored in this paper. Random scheduling is computationally simple, whereas optimal scheduling is currently very difficult. We have found, using a traffic model appropriate for circuit switched traffic that increases of typically 10 to 15 percent in offered load can be obtained through optimal scheduling (as compared to the much simpler random scheduling algorithm). The improvement is a function of the number of time slots (or circuits) per time-multiplexed frame, and falls to zero for both very small and very large frame sizes. Thus, in many circuit switching applications, providing a computationally expensive optimal schedule may not be warranted. This conclusion has important ramifications for both electronic and emerging photonic switching systems since it reduces the importance of the costly design feature of optimal scheduling.

Combined circuit switch and packet switching system

Abstract: Apparatus (FIG. 3) for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus (320). A memory (l04C) having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve circuit switch information or packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus. Packet data can be inserted into each time slot not presently being used by the circuit switch. A special information bit is inserted into each time slot to specify whether the remainder of the bits of the time slot represents circuit switch or packet information. The information bit is used by the receiving apparatus to steer the bits of each time slot to either a receiving circuit switch or a receiving packet switch.

Line switching control system for mobile communication

Abstract: A line switching control system effects switching between a data communication mode and a voice communication mode in mobile communication, particularly mobile telephone service. The line switching control system includes a transmitter/receiver unit for transmitting and receiving signals through an antenna, an input device combined with a telephone, a switching device for effecting switching between the data communication mode and the voice communication mode, and a control unit for controlling switching between the data communication mode and the voice communication mode based on a mode switching command entered through the input device. When a key of the input device at the user's hand is depressed, switching between the data communication mode and the voice communication mode can smoothly be performed.

Control information communication arrangement for a distributed control switching system

Abstract: A switching system (10) including a number of switching modules (1000, 1020, 1050) each having a plurality of access ports (P1, P2, P9, P5). Incoming and outgoing packet channels (81, 82) are extended between each switching module and an inter-module packet switch (2012). Each of the switching modules includes both a packet switching unit (1400) and a circuit switching unit (1011) for switching information to and from the access ports. Each switching module further includes a control unit (1017) that controls the switching units and that generates inter-module conyrol packets, and a communication interface (1900) that transmits inter-module control packets generated by the control unit on the incoming packet channel to the inter-module packet switch. The communication interface also transmits inter-module control packets received on the outgoing packet channel from the inter-module packet switch to the control unit. The inter-module packet switch concurrently packet switches inter-module control packets received on a number of the incoming packet channels, via multiple independent paths (2001, 2002, 2003) to a number of the outgoing packet channels.

Data transfer control system

Abstract: The data transmission control system includes a transmitter/receiver data buffer for temporarily storing data transmitted to or from a ring transmission line, a basic clock generating device for generating a basic clock and its phase data to be transmitted in a packet to the next node to synchronize a basic clock of the next node, and a controller for controlling data storage of the data buffer and timing of data transmission to the ring transmission line so as to produce a constant transmission time, thus making it possible to use a circuit switching method in the token ring network.

Time division circuit switch

Abstract: A time-division circuit switch which serves as a cross connect for time multiplexed signals including frames subdivided into slots serves to cross-connect input and output lines on a slot-by-slot basis. The circuit utilizes a self-routing packet switching network. An input interface attached to each input line converts incoming slots into fixed length packets which can be routed through the self-routing switching network in a synchronous manner. An output interface coupled to each output line reconverts the packets into slot/frame format. To prevent blocking, the self-routing packet switching network runs at a faster rate than the input and output lines of the switch.

One-Dimensional Circuit-Switched Networks

Abstract: This paper is concerned with the stationary distribution of a one-dimensional circuit-switched network. We show that if arrival rates decay geometrically with distance, then under the stationary distribution the number of circuits busy on successive links of the network at a fixed point in time is a Markov chain. When each link of the network has unit capacity we show that translation invariant arrival rates lead to a stationary distribution which can be described in terms of an alternating renewal process.

Radio transceiver including and antenna switching circuit capable of changing reception sensitivity

Abstract: A radio transceiver comprises an antenna, a transmitter, a receiver, an antenna switching circuit including switching diodes for coupling said trans­mitter and said receiver to said antenna in response to a transmit mode and a receive mode, respectively, and means for changing the resistances of said switching diodes in response to another receive mode to reduce the level of a received signal supplied from said antenna to said receiver.

High-Speed Packet Switching Systems for Multimedia Communications

Abstract: High-speed packet switching (HPS) systems can Provide flexible, economical, high-quaiity services for integrated voice, video, and data communications. To realize such HPS systems, methods have been developed to bring about high-speed protocol processing as well as a system architecture for facilitating high-throughput switching. Adopting the parallel processing algorithm into protocol processing allows us to achieve high-speed packet protocol processing of about 100 times faster than conventional processing. Furthermore, a fully distributed system architecture in addition to hierarchical interconnection networks can achieve high-capacity packet switching systems. The proposed HPS system is thus capable of accommodating lines of up to 10-50 Mbits/s, of providing high-throughput switching capability of 1 000 000 packets/s, and of having an average delay of less than 2 ms. Furthermore, an evaluation of network delay performances of video conferencing and voice communications indicate that HPS systems are quite suitable for handling such multimedia communications.

A new broadcast switching network

Abstract: A rearrangeable broadcast switching network is proposed. Under the condition that the number of outlets (customers) is much larger that the number of source inlets (video channels), the network normally has fewer switching nodes than other approaches. The approach is based on the decomposition of the multiconnection function into two subfunction: consecutive spreading and routing. I offers modular construction, easy growth, and an easy path hunt. The network is especially suitable for the directional-coupler photonic-switching technology and an implementation based on this technology is presented. The number of crosspoints required for electronic and photonic implementations is compared. >

CMOS VLSI Applications in Broadband Circuit Switching

Abstract: The circuit switching fabric for broadband networks will demand numerous densely interconnected components, with channel rates as high as 150 Mbit/s, This is a natural application area for VLSI, which motivates the evaluation of the key technologies and requirements for realizable broadband circuit and packet switching systems. The critical circuit switching capabilities include the basic crosspoint array, I/O interface between circuit packs, jitter removal and regeneration, and multichannel phase alignment. This paper describes results obtained in these four critical areas. With remote multiplexing units, the greatest constraints are power dissipation and system volume. CMOS circuitry has the advantage here, because of its intrinsic usage-sensitive low power operation. The challenge is to prove that CMOS processes and designs are compatible with the high data and clock rates required of broadband ISDN systems. A fully connected 16 × 16 crosspoint array has been implemented by several laboratories. In this paper we will report on our asynchronous 16 × 16 switching chips fabricated in a 2 μm CMOS process. These devices support channel rates of up to 240 Mbit/s. Crosstalk, jitter accumulation, and power dissipation dominate system issues at the IC interface, making simple CMOS or TTL signaling inappropriate for broadband applications. We will discuss the ECL compatible signaling used in our broadband CMOS IC's. This low noise interface is currently operating at 150-200 MHz rates. We will stress the resulting improvement in noise and jitter accumulation. We will also consider a broader class of low power signaling schemes, including CMOS to GaAsFET direct interfacing. The physical design of switching fabric components will be at least as important as the electronics. Our custom high-density chip carrier and surface mounting arrangement will be discussed, which offers a fourfold reduction in parasitic inductance and capacitance, with corresponding reductions in crosstalk, jitter, and interconnect power dissipation. Pulses normally degrade after passing through asynchronous crosspoint elements. A scalable switching fabric must include regeneration to control this accumulated noise and jitter. We have demonstrated the critical components of such a regenerator, including VCO's, process independent digital phase shifters, phase error detectors, and data relocking circuitry. Existing CMOS technology can support the circuit switching requirements for broadband networks. A thorough understanding of the interface capabilities and requirements will be necessary to deliver functional hardware. The knowledge gained in this work will have direct application to packet switch constraints and performance.

Packet switching network

Abstract: Packet switching network with first (DN) and second (RN) cascaded parts including first and second switching modules respectively In the second switching modules the path selection is controlled by routing information contained in the packets In the first switching modules this selection is performed without using routing information only for a path set up packet, whilst for the following packets use is made of routing information on the route followed by the path set up packet Each module decides to multiplex an input stream on an output only when a calculated traffic load is smaller than a limit value This load is calculated from traffic load parameters contained in the path set up packet

Automatic telecommunication switching system

Abstract: An automatic telecommunication switching system handles all communications, whether voice or data, in packet switching manner. The switching network consists of a multi-stage network of co-ordinate matrix elements each of which has memory and processing means. Such an element is a single-chip VLSI device. Each packet has a header which includes the address of the network outlet to which that packet is to be routed, each such address consisting of a digit for each stage via which the packet is to be routed. At each matrix element the appropriate digit of that address is used to route the packet to the appropriate outlet from the matrix element.

Fiber distributed data interface

Abstract: The Fiber Distributed Data Interface (FDDI) is a proposed American National Standard tor a 100-Mb/s token ring using an optical fiber medium. Default values of timers have been chosen to provide for networks of 500 stations using 100 km of duplex fiber cable. The highly efficient ring topology and protocols chosen allow sustained data rates exceeding 10 Mbytes/s.

Transmitter for isdn s-bus interface circuit

Abstract: In the future ISDN network up to eight subscriber terminals for speech, data and image traffic can be connected to the network terminating circuit (NT). The interface between the subscriber terminals and the network terminating circuit - the S-interface - is specified in CCITT Recommendation I.43O. The transmitter in the S-­interface must satisfy many, sometimes conflicting, requirements. This is satisfied to an optimum extent by providing the transmitter with a bridge circuit formed by semiconductor switching elements which are controlled by a digital control circuit. According to the invention the output current of the transmitter is maintained substantially constant with the aid of a differential amplifier connected to the bridge circuit.

Switching techniques for fdm communication systems

Abstract: The present invention relates to a switching technique for packet Frequency Division Multiplexed (FDM) communication systems. In the present system, each of N system users is assigned (a) either a separate fixed one of N transmit frequency channels or a selected free one of L transmit frequency channel for communications to a head-end FDM channel switching arrangement (IO), and (b) a fixed assigned separate one of N receive channels for communications from the head-end FDM channels switching arrangement. At the FDM channel switching means, all FDM channel signals received from the system users are directed into separate paths (21) through the switching arrangement. The signals in each path are demodulated (23) to baseband, and a destination address in each packet is detected (28) to determine where each packet is to be sent. Each path in the switching arrangement is hardwired therethrough to an associated transmitting oscillator (29) which is frequency tuned, by means of the detected destination address, to the unique frequency channel of the user or the external network which is the desired destination of the packet. Thus, switching of a packet signal is accomplished without ever connecting or disconnecting wire lines.

Quasi-stationary distributions and one-dimensional circuit-switched networks

Abstract: We discuss the quasi-stationary distribution obtained when a simple birth and death process is conditioned on never exceeding K. An application of this model to one-dimensional circuit-switched communication networks is described, and some special cases examined. BIRTH AND DEATH PROCESSES; COMMUNICATION NETWORKS

Synchronous Composite Packet Switching-A Switching Architecture for Broadband ISDN

Abstract: A new switching architecture for broadband ISDN, "Synchronous Composite Packet Switching (SCPS)," is proposed and evaluated. It efficiently integrates circuit and packet switching functions on a single switching system and accommodates very high speed-up to several tens of Mbit/s-communication services, such as very high speed bursts of data, still picture, and motion video, as well as 64 kbit/s or less voice and data services. The SCPS system comprises plural switch modules and plural Very high speed synchronous loops. In the SCPS system, messages on plural circuit switched channels are assembled into quasi-packets, called "composite packets," and switched synchronously between switch modules, maintaining complete time transparency and short absolute delay time. A system parameter design to obtain high system efficiency and appropriate system modularity is explained, and an example for a very large capacity transit switch of 4 Gbit/s throughput is presented. System implementation problems to realize the SCPS principle, such as efficient implementation of the composite packet assembling and loop transmission functions, are investigated and an experimental system constructed for circuit switching part is presented. The most remarkable characteristic of the SCPS is that it efficiently integrates 64 \times n kbit/s circuit switching with packet switching. Moreover, the SCPS system retains compatibility with existing networks and the possibiliy of evolution toward a future broadband ISDN. On the basis of the above investigations and experimental system construction, the authors conclude that the SCPS is one of the most practical switching architectures for the coming broadband ISDN era.