Showing papers on "Clock domain crossing published in 1998"

Delay locked loop circuitry for clock delay adjustment

Abstract: Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same

Abstract: A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to store the digital signal responsive to the clock signal. The digital signal is applied to the latch, and stored in the latch responsive to the clock signal. The digital signal stored in the latch is evaluated to determine if the stored digital signal has an expected value. The timing offset of the digital signal is thereafter adjusted relative to the clock signal. and the digital signal is once again stored in the latch responsive to the clock signal at the new timing offset. A number of digital signals at respective timing offsets relative to the clock signal are stored and evaluated, and a final timing offset of the digital signal is selected from the ones of the timing offsets that cause the latch to store the digital signal having the expected value. The timing offset of the digital signal is thereafter adjusted to the selected final timing offset. A read synchronization circuit may adaptively adjust the timing offset of digital signals in this manner, and such a read synchronization circuit may be utilized in many types of integrated circuits, including packetized dynamic random access memories, memory systems including a memory controller and one or more such packetized dynamic random access memories, and in computer systems including a plurality of such packetized dynamic random access memories.

Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system

Abstract: A semiconductor integrated circuit device (20) has a command decoder (1) for issuing a control command (CNT) in accordance with a supplied control signal, a DRAM core (3), and a timing adjusting circuit (22) for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core (3). The timing adjusting circuit (22) generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock (CLKi), and generates the DRAM control signal (CNT) by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Clocking design and analysis for a 600 MHz Alpha microprocessor

Abstract: The clocking methodology for the 600 MHz Alpha microprocessor allows increased performance goals to be met through multi-level buffering. In addition power savings are realized through reduced metal usage and conditional clocks. Two distinct analysis methods are required to verify the clock design. One is used for large, globally distributed clocks and the other is applied to small, locally distributed clocks. The clock is generated from an 80-200 MHz reference clock multiplied by an on-chip phase-locked loop (PLL) to a nominal frequency of 600 MHz. The clock distribution network up to and including the global clock (GCLK) is included in the feedback loop of the PLL to control phase alignment. GCLK is the primary timing reference for the chip. The generation of GCLK begins at the PLL and is routed through a high-gain buffer network to a central point on the die. From there the clock is driven through buffered X, H and RC trees to distributed GCLK drivers located in a windowpane pattern across the chip. The final physical stage of the global clock distribution network is a grid of upper-level low-impedance metal that covers the entire die.

System and method of computer operating mode clock control for power consumption reduction

Abstract: An activity sensing power reduction and conservation apparatus, system, and method for a computer system. The computer system has resources including a processor, a memory, and an input/output device, and an operating system for controlling the resources. At least one of the resources can be placed into in any one of three operating modes including a first mode having a first power consumption level, a second mode having a second power consumption level less than the first level, and a third mode having a third level less than the second level. The first mode may be characterized by maintaining clocking of the processor at a first clock frequency, the second mode by clocking the processor at a second clock frequency less than the first frequency or by not maintaining clocking of the processor, and the third mode by maintaining operation of the memory to preserve the integrity of any stored memory contents. During operation of the computer system in the first mode, activity is monitored to detect completion of idle threads executing on the system, and the processor clock is slowed or stopped to at least that one resource in response to the idle thread completion detection. During operation in the second mode where the processor clock is slowed or stopped, a slow or stop resource command is generated to slow or turn off clock signal to at least one of the resources in response to occurrence of a timeout condition indication received from a timer circuit.

Power control system for synchronous memory device

Abstract: A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same

Abstract: A system for adjusting the phase of an internal clock signal relative to an external clock signal in a packetized dynamic random access memory device. The system applies a plurality of initialization packets to the memory device that are captured in a shift register responsive to a transition of the internal clock signal. However, the phase of the internal clock signal is sequentially incremented after each initialization packet has been captured in the shift register. After a plurality of initialization packets have been captured, an evalution circuit identifies which phases of the internal clock signal clocked the shift register at the proper time to accurately capture each initialization packet. A single phase of the internal clock signal is then selected from within the range of internal clock signal phases that successfully captured initialization packets. This selected phase of the internal clock signal is used during normal operation of the memory device.

Clock distribution network

Abstract: A method and an apparatus for providing an optical clock distribution network. In one embodiment, an optical source is configured to emit optical pulses at a desired clock frequency. The optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die. In one embodiment, each clock receiver node locally generates a photocurrent in response to the split optical beams. Each of the photocurrents is locally converted into voltage and thus into local clock signals, which are used to clock the local area of the integrated circuit. In one embodiment, the semiconductor die includes an additional clock receiver node used to clock a clock generation circuit included in the semiconductor die. The clock generation circuit generates clock signals that are in phase with each other and the other clock signals generated throughout the semiconductor die. In one embodiment, the clock signals generated by the clock generation circuit are used to clock and phase lock input/output communications on the semiconductor die as well as off chip input/output communications between the semiconductor die and other external semiconductor dice of the system.

Digital delay locked loop

Abstract: An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is synchronized with a reference clock signal by propagating the reference clock signal through a variable digital delay path. A wide phase detection region surrounds a selected rising edge of the internal clock signal. The DLL loop is open as long as the internal clock signal and a target edge of the reference clock signal are not simultaneously within the phase detection region. To achieve a DLL locked condition, the variable delay is increased from a minimum setting until the edge of the phase detection region is shifted in time just past the target edge of the reference clock. Once the DLL loop has been closed, a clock jitter filter is enabled to reject reference clock jitter effects on the DLL locked condition. A digital phase detector controls the delay line propagation delay to establish synchronization between the internal clock and the reference clock. Unused delay elements within the variable delay path are deactivated to save power.

Method and apparatus for clock skew compensation

Abstract: A method and apparatus to compensate for skew in a processor clock signal. A first clock signal at a first location in the processor is compared with a reference clock signal. The first clock signal is corrected based on the results of this comparison with the reference clock signal. The clock signal may be corrected by using a programmable delay compensator. A second clock signal at a second location in the processor may be compared with the corrected first clock signal and the second clock signal may be corrected based on the results of the comparison. The compensators may be permanently programmed as required using fuses associated with compensator control bits.

Timing synchronization and switchover in a network switch

Abstract: A data communications switch and method of operation are presently disclosed enabling flexible, selectable provision of a common timing signal for synchronized external communication through physical layer interfaces with other network devices, synchronized internal communications within the switch, and for uninterrupted synchronization of such communications. Synchronization of external communications is enabled by programmable selection from among plural potential timing references at redundant timing modules (TMs). An active TM (12a) provides a primary external synchronization clock; a standby TM (12b) provides a redundant timing function. Both TMs (12a and 12b) access the same references. A state signal indicates which synchronization clock is active. External interfaces derive timing from this distributed clock. Synchronized internal timing is provided by an internal clock (24) and phase-locked loop (PLL) on each TM (12a and 12b). The clock/PLL timing signal output is routed to other switch elements, enabling synchronized internal data transfer. Both interconnected TMs (12a and 12b) actively generate clock signals for external and internal use, enabling seamless timing switchover should conditions warrant a change in TMs (12a and 12b).

Information processing apparatus with CPU-load-based clock frequency

Abstract: An information processing apparatus includes a CPU, a memory, and a reference signal generator and operates based on a system clock signal generated by the reference signal generator. The apparatus includes a detection unit for detecting a CPU operational state and a clock control unit for controlling frequency of the system clock signal. The detection unit detects a CPU busy ratio as a CPU operational state indicating the load on the CPU. The clock control unit controls the frequency of the system clock so that the detected CPU busy ratio falls within a permissible range of CPA load.

Oscillator with clock output inhibition control

Abstract: An oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator, two independent current generators, a transition detector and a clock inhibitor. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current that is independent of temperature. The oscillator is capable of three modes of operation: fast mode, slow/low power mode and sleep mode, which are controlled by the transition detector in response to external control signals. When the transition detector transitions from one mode to another, it controls the clock inhibitor to block a clock output of the oscillator generator for a predetermined number of clock cycles to allow the clock output to stabilize. The oscillator is implemented on a single, monolithic integrated circuit.

Power saving scheme for a digital wireless communications terminal

Abstract: According to the present invention, a mobile communications terminal includes a high accuracy clock for providing a timebase in a normal operating mode, a "slow clock" for providing the timebase in a low power mode of operation, and at least one processor coupled to the high accuracy clock and the "slow clock" for controlling the modes of operation. In a preferred embodiment, the mobile communications terminal includes a conversion signal processor (CSP), a digital signal processor (DSP), a communications protocol processor, and a radio frequency (RF) segment. The CSP, which includes a plurality of registers, interfaces with the DSP to execute the timing control functions for the terminal. In the normal operating mode, the timebase is maintained from the high accuracy clock. During inactive periods of terminal operation (e.g., in a paging mode), a sleep mode is enabled wherein the high accuracy clock source is disabled, the DSP, CSP, and communications protocol processor are shut down, and the "slow clock" provides the timebase for the terminal while a sleep counter is decremented for a given sleep interval. Upon expiration of the sleep interval or in response to an intervening external event (e.g., a keypad is depressed), a terminal wake-up is initiated so that the high accuracy clock resumes control of the timebase. Because the high accuracy clock and the "slow clock" are not synchronized, the CSP and DSP calibrate the "slow clock" to the high accuracy clock prior to the terminal entering the sleep mode.

Method and apparatus for time synchronization in a communication system

Abstract: A method and apparatus for time synchronization in a communications system such as a system including cable modems is provided. The synchronization method comprises the steps of receiving a first timestamp from a headend unit with the cable modem, and generating a first cable modem time reference with the cable modem in response to the receipt of the first timestamp. The cable modem then receives a second timestamp from the headend unit and generates a second cable modem time reference in response to the receipt of the second timestamp. A headend difference time comprising the difference of the first and second timestamps is then generated as is a cable modem difference time comprising the difference of the first and second cable modem time references. A clock error time that comprises the difference of the headend difference time and the cable modem difference time is then generated as well as a correction factor in response to the clock error time. The local clock of the cable modem is then synchronized with the master clock of the headend unit through the adjusting of the output of the local clock output in response to the correction factor. The correction factor in one instance comprises an offset value representative of the amount of clock error per local clock pulse. This offset value is added to an accumulator on each local clock pulse, and the local clock output is adjusted when the accumulator rolls over. The synchronized clock signal can then be utilized to determine a time slot in which the cable modem can transmit an upstream signal to the headend without colliding the upstream signal with upstream signals from other modems in the system.

An adaptive digital deskewing circuit for clock distribution networks

Abstract: As clock frequency in CPU designs increases, skew management in the clock network becomes more important Clock skew reduces the performance of the design and is a function of load, network distribution across the die, and device mismatch as well as temperature, and voltage gradients This digital deskewing circuit can be used in microprocessor designs to equalize two clock distribution spines by compensating for these mismatches and gradients The circuit is composed of delay lines in both spines of the microprocessor clock distribution network, a phase detection circuit, and a controller The phase detection circuit determines the phase relationship between the two spines and generates an output based on the phase relationship The controller takes the phase detection information and makes a discrete adjustment to one of the delay lines that was determined by the controller to require adjustment

A high-speed, low-power clock generator for a microprocessor application

Abstract: This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment. A dedicated on-chip voltage regulator based on a bandgap reference has been designed to reduce the effect of supply noise on the clock generator. To avoid a large voltage drop across the power-supply bond wires during the startup sequence, the core frequency can be increased by steps in one period of the core clock, with a limited frequency overshoot and no missing pulses. The circuit has been implemented in a CMOS 0.35 /spl mu/m process. The voltage-controlled-oscillator frequency range is between 350 MHz and 2.8 GHz, with a peak-to-peak cycle-to-cycle jitter lower than 16 ps. While booting Unix on a system, the maximum phase misalignment is lower than /spl plusmn/100 ps.

Method for aligning clock and data signals received from a RAM

Abstract: One embodiment of the present invention provides a method for aligning a data signal and a data clock signal received from a memory during a read operation. The method includes receiving the data signal and the data clock signal from the memory, and determining an offset between these signals. If the offset is outside of a valid range, the system adjusts a delay between the data clock signal and the data signal. In a variation on the above embodiment, the method is performed by special-purpose hardware located in a memory controller, and operates periodically while the computer system is running. In another variation, the method is carried out by a BIOS program stored in read only memory, and operates during system startup.

Method and apparatus for distributing an optical clock in an integrated circuit

Abstract: A method and an apparatus for optically clocking an integrated circuit in a semiconductor. In one embodiment, a laser is configured to emit infrared laser pulses at a desired clock frequency. The laser pulses are separated into a plurality of split laser pulses, each of which are focused through the back side of a C4 packaged integrated circuit die into P-N junctions distributed throughout the integrated circuit die. Each P-N junction locally generates a photocurrent in response to the split laser beams. Each of the photocurrents are locally converted into voltages and thus into local clock signals, which are used to clock the local area of the integrated circuit. With the presently described optical clocking technique, the local clock signals have extremely low clock skew. The presently described technique may be employed in integrated circuits system-wide, in multi-chip modules, or in an individual integrated circuit. By removing the global clock distribution network from the silicon, the present invention allows chip area used in the prior art for a global clock distribution networks to be used instead for signal routing or allows overall die sizes to be reduced.

Synchronous clock generator including delay-locked loop

Abstract: A data and command latching circuit (60) includes a delay-locked loop (62) driven by a continuous reference clock signal (CCLKREF) that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit (60) also includes a variable delay circuit (64) external to the delay-locked loop (62) that is driven by a discontinuous reference clock signal (DCLKREF). Delay of the external delay circuit (64) is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal (CCLKREF). The delayed clock signals from the delay-locked loop activate control data latches (66) to latch control data (CD1-CDN) arriving at the latch circuit (60). The delayed signals from the variable delay circuit (64) activate data latches (68) to latch data (DA1-DAM) arriving at the latch circuit (60).

Apparatus for aligning clock and data signals received from a RAM

Abstract: One embodiment of the present invention provides an apparatus for aligning a data signal and a data clock signal received from a memory during a read operation. The apparatus includes a data input for receiving the data signal, and a clock input for receiving the data clock signal. The data signal and the data clock signal feed into an offset mechanism that determines an offset between the data clock signal and the data signal. This offset feeds into a comparison mechanism that determines if the offset is outside of a valid range. If the offset is outside of the valid range, an adjustment mechanism adjusts a delay between the data clock signal and the data signal. In a variation on the above embodiment, the apparatus is implemented in special-purpose hardware within a memory controller, and operates periodically while the computer system is running. In another variation, the apparatus is implemented as part of a system BIOS program stored in read only memory and operates during system startup.

Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices

Abstract: A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.

Low skew clock tree circuit using variable threshold voltage transistor

Abstract: PROBLEM TO BE SOLVED: To provide a clock tree circuit capable of controlling clock skew of a clock tree circuit, reduced in power consumption and low in clock skew SOLUTION: This clock tree circuit uses a transistor having a threshold voltage variable well structure for a clock element Here, it has phase comparator circuits 31 to 33 which perform comparison observation of skew values among respective elements 21 to 24 and output differential voltage and charge pump circuits 41 to 43 which make the differential voltage of the circuits 31 to 33 inputs and supply them as well potential to each well terminal of the elements 21 to 24, controls the switching speed of a clock tree circuit by adjusting the threshold voltage of each element 21 to 24 and reduces clock skew

Precise, low-jitter fractional divider using counter of rotating clock phases

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock. Any phase difference charges a loop filter and changes an adjustment voltage. The adjustment voltage changes the delays in the delay line so that the sum of all delays in the delay line matches the clock period. Since smaller count values can be used when fractional rather than whole-number divisors are used, phase comparisons in a PLL are increased, reducing jitter and smoothing the output.

Clock latency compensation circuit for DDR timing

Abstract: A clock latency circuit, method and system is provided which allows the synchronization of data according to the rising and falling edges of a system clock.

Method and apparatus for pipelining data in an integrated circuit

Abstract: A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.

Clock supply circuit

Abstract: A clock dividing section receives a system clock and generates and outputs clock signals of two or more types. Selectors select any of the clock signals of two or more types outputted by the clock dividing section and feed it to a printing control block or reading control block. A decision divider monitors operational states of each block and gives control so that a frequency to be supplied to a functional block in an idle state where any operation is not required is lower than that to be supplied to a functional block being in an active state. Power consumption of the whole custom IC can be more reduced compared with a configuration wherein a clock of fixed frequency is constantly supplied to each functional block and a noise can be controlled.

Interconnect structure for FPGA with configurable delay locked loop

Abstract: A field programmable gate array (FPGA) is provided that includes a plurality of pads and a plurality of delay locked loops (DLLs). Programmable connections enable any one of the DLLs to have multiple pads as inputs. Programmable connections also enable the DLLs to be selectively connected to one another. Programmable connections further enable the pads to be selectively connected to general interconnect circuitry or global clock drivers of the FPGA. Programmable connections are also provided for selectively connecting the DLLs to the global clock drivers. This FPGA structure enables the pads to be configured to receive either clock or non-clock signals. This structure also enables the FPGA to operate as a clock mirror, and to generate one clock signal from another clock signal on the FPGA.

Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing

Abstract: A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

Clock and data recovery scheme for multi-channel data communications receivers

Abstract: The multiple-channel clock and data recovery scheme of the present invention derives a single clock signal from multiple mis-matched data streams. The single clock is phased to provide a clocking signal such that the data sampler of the clock and data recovery scheme performs bit center sampling of the data at the bit center average of all channels. The phase of the recovery clock is the average of all the data stream phases, and is the optimal sampling phase for minimum combined bit error rate of all the channels.