Showing papers on "CMOS published in 1974"

CMOS voltage controlled oscillator

Abstract: A CMOS voltage controlled oscillator is described. This CMOS voltage controlled oscillator is a linear CMOS circuit and exhibits an infinite current gain, a near infinite input impedance, a very high voltage gain with a corresponding low power consumption. Additionally, the oscillator is capable of operating over a wide range of DC supply voltages. Because the circuit is of CMOS design its complexity is much less than corresponding circuits made using bipolar devices or field effect transistors. This CMOS voltage controlled oscillator comprises a complementary current source generator for providing a current source as a charging current and a current sink as a discharging current of equal magnitude for the timing capacitor of the circuit. This charging and discharging current are each linearly proportional to the input controlling voltage. A high speed voltage comparator is responsive to the voltage of the timing capacitor and the voltage from an hysteresis feedback circuit for providing fast acting driving voltage for the output stage. A linear amplifier output stage is responsive to the high speed voltage comparator for providing ultra-fast changing signals for wave shaping purposes. An hysteresis feedback loop responsive to the output stage and connected as one input to the voltage comparator provides two threshold states for the voltage comparator.

Threshold logic using complementary mos device

Abstract: Complementary MOS (CMOS) devices form a plurality of threshold gate configurations having majority logic functions with near symmetrical switch delay times. Corresponding gate terminals of individual MOS devices within identical N and P channel complementary networks are commonly connected and adapted to receive input signals. Operating voltages are connected to the respective sources of the N and P channel networks and the network drains are commonly connected to provide an output.

CMOS synchronous binary counter

Abstract: A multi-state CMOS synchronous binary counter is implemented utilizing a CMOS transmission gate look-ahead carry circuit requiring only a fraction of the area required for AND or NAND gate carry structures.

Complementary FET pulse level converter

Abstract: An interfacing circuit for restoring voltage pulses to a desired fixed level. The circuit is particularly adapted to CMOS technology and includes features which result in rapid output rise and fall times, latching of the output voltage level, and isolation of the input following transition of the input voltage between its respective final levels. The circuit is also relatively insensitive to noise since it requires voltage transitions greater than the FET threshold levels to fully activate and switch the latching circuit means.

Radiation hardening of CMOS/SOS integrated circuits

Abstract: Radiation tolerant CMOS circuits can be made by building them in a thin film of silicon-on-sapphire (SOS) with a hard gate dielectric. Radiation effects in MOS devices are reviewed, and the problems associated with radiation tolerant CMOS/SOS devices are described. Some gate dielectric techniques which show promise in hardening CMOS circuits are presented, and the radiation behavior of Al 2 O 3 gate dielectrics are described.

Rapid annealing in irradiated CMOS transistors

Abstract: Data characterizing the transient annealing of the gate threshold voltage of contemporary CMOS transistors following exposure to pulsed ionizing radiation are presented and discussed. Devices tested during the study include those fabricated on both bulk silicon and silicon-on-sapphire substrates. Silicon dioxide and aluminum oxide gate dielectrics are evaluated. Leakage current phenomena associated with charge formation in dielectric substrates or dielectric isolation layers are also considered.

Implementation of 3-valued logic with c.o.s.m.o.s. integrated circuits

Abstract: Two ternary gates realising basic ternary operators (ternary NOR, NAND and invertors) are designed with c.o.s.m.o.s. integrated circuits. Any one of these gates may be used to implement several 3-valued algebras.

Transient and steady-state radiation response of CMOS/SOS devices

Abstract: In an investigation to characterize the radiation properties of a pilot line product capability for manufacture of MNOS memory arrays, a CMOS test vehicle proposed as the building block for the array electronics was tested in a nuclear environment. The test device was a CD4007 configuration fabricated with an unhardened SiO 2 gate insulator on a sapphire substrate. Test devices were made with aluminum and silicon gates, and test samples were selected to satisfy the requirement of operating satisfactorily with a source-drain voltage ≤21.5 volts. All tests were conducted with a drain-source voltage of 20 volts and gate biases in the range of 0 to 20 volts. The tests were as follows: (1) transient photo-current, (2) transient annealing, (3) total dose, (4) survivability, and (5) neutrons. Facilities at AFCRL were used for the first four and the Aberdeen Pulse Reactor for the last test. The tests were conducted in the order listed above on different batches of samples for each test.

CMOS Boolean logic mechanization

Abstract: Unique, relatively simplified circuits employing complementary metal oxide semiconductor transistors and suitable diode means to mechanize the Boolean functions A.sup.. B and A+B and combinations thereof. In a preferred embodiment, the transistors and diodes may be fabricated by silicon-on-sapphire integrated circuit techniques. The circuits obviate the need for a conventional NOR or NAND gate which is common to logic gating arrangements of the prior art. Hence, the number of components and the corresponding cost of the circuit are reduced while the operating speed thereof is increased.

High-voltage simultaneous diffusion silicon-gate CMOS

Abstract: A complementary metal-oxide-semiconductor fabrication process has been developed for low-power-consumption biomedical applications. This process realizes low gate-drain and gate-source capacitances useful for high-speed low-capacitive coupling noise circuitry, on the same integrated circuit die with high-voltage p-channel transistors capable of withstanding greater than 75V. Details of the process and device parameters and experimental correlations relating these two parameters are given. A high-voltage driver scan circuit is presented as an example of the capability of this process.

Siucon-on-sapphire device photoconduction predictions

Abstract: The linear sapphire photoconductance approximation was used to model dose-rate effects in CMOS/SOS inverters. From this model, optimum values were derived for the ratio of n-channel to p-channel transistor gate width, thereby maximizing the dose-rate failure threshold.

High-density static ESFI MOS memory cells

Abstract: The area of static MOS memory cells is reduced by avoiding crossovers in the flip-flop, and by selecting the cell by a diode. Such cells have been realized in epitaxial silicon films on insulators (ESFI) with complementary transistors, diodes, and high-rated load resistors; the cell areas can be as small as 1500 /spl mu/m/SUP 2/ (2.4 mil/SUP 2/), and are the smallest areas of static MOS memory cells known so far. The static and dynamic behavior of these cells are discussed, as well as their behavior in a large-scale integrated (LSI) circuit; for this purpose an exploratory memory with 4096 bits and with simple decoding and sensing circuitry has been realized on an area of 3.5/spl times/4.2 mm (140/spl times/170 mils). Taking into account the measured data, an ESFI MOS memory circuit shows a better performance in speed and power dissipation than dynamic MOS memories, but its principal advantage is the static operation mode.

EMP hardened CMOS circuits

Abstract: This paper shows how CMOS integrated circuits can be protected against electrical transients originating from nuclear explosions, static discharge, etc. First, the causes of transient failures are determined and then analyzed. Next, a wide range of protection devices are designed and evaluated. Finally, complete transient hardened logic gates are fabricated and tested to prove the feasibility of EMP hardened CMOS circuits.

Method of achieving semiconductor substrates having similar surface resistivity

Abstract: A method of achieving semiconductor substrates having similar surface resistivity comprises implanting ions into semiconductor substrates of very high resistivity and then, preferably, subjecting the substrates to a drive-in diffusion. This method can be utilized in the manufacture of CMOS integrated circuits to achieve transistors having closely matched threshold voltages.

Invited: Integrated injection logic - A new approach to LSI

Abstract: Integrated injection logic found to afford lateral PNP transistors as current sources and multicollector NPN transistors as inverters will be discussed. Packing densities of 400 gates/mm2and speed power products of 0.13 pJ have been realized. Comparison with MOS logic will be offered.

A CMOS 10-bit D/A converter

Abstract: A fast monolithic 10-bit, one, two or four-quadrant multiplying D/A converter has been developed. Using CMOS, thin film, low-power technology, the major error sources of earlier monolithic designs have been found to be avoided.

CMOS/bipolar linear integrated circuits

Abstract: A simple, high-performance operational amplifier using an economical monolithic CMOS/bipolar process will be described, and circuit components, layout and performance discussed.

Local oxidation of silicon/CMOS: Technology/design system for LSI in CMOS

Abstract: The LOCMOS process and its ability to increase packing density and reduce cost of LSI CMOS circuits will be presented. A computer-aided layout system which can be used for wildlogic circuits using this technology will also be described.

CMOS/SOS for electronic watch applications

Abstract: Crystal-controlled watch circuits using CMOS/SOS technology will be discussed. The low-power high-speed features of this technology allows the use of less costly, high-frequency, thermally-stable, AT-cut quartz crystals. Circuits have operated at 1.4 V/4 MHz, consuming less than 12μW.

Cmos flip flop memory element without crossover, and method of operation

Abstract: A B S T R A C T A static semiconductor storage element includes a flip-flop formed of a pair of complementary field effect transistors which are cross coupled without intersection to form a bistable circuit. One node of the flip-flop is connected to a terminal which is employed for both reading and writing functions. The flip-flop is set or reset by connection of an appropri-ate voltage to the node, and nondestructive read out is carried out by sensing the voltage level of the node.

Design of NAND logic switching circuits

Abstract: Problems in switching theory can be solved using universal NAND logic elements. The design of these circuits is optimized by using a factor procedure to ensure gate minimality with specified fan-in restrictions. The method suggested provides a means of obtaining hand solutions and can be suitably adapted for computer programming.