Showing papers on "Comparator applications published in 2005"

High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Capacitance sensor using relaxation oscillators

Abstract: An apparatus that may be used to sense capacitance, as well as other functions. The apparatus includes a comparator circuit with hysteresis, a capacitor, and a current driver. The comparator circuit with hysteresis includes a first input and an output. The capacitor is coupled to the first input of the comparator circuit with hysteresis. The current driver is coupled to the output of the comparator circuit with hysteresis and to the capacitor. The current driver reciprocally sources and sinks a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential. The current driver is responsive to the output of the comparator circuit with hysteresis.

Low-voltage high-speed Schmitt trigger and compact window comparator

Abstract: Gates with input hysteresis are often necessary in circuits operating in noisy environments. Described is a very simple CMOS Schmitt trigger circuit, well suited for low-voltage and high-speed applications. The circuit also allows the construction of a very compact window comparator.

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

Abstract: A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-/spl mu/m standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10/sup -12/ by laboratory measurements.

AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus

Abstract: In a solid-state imaging device including an analog-to-digital converter, a clock converter that generates a high-speed clock that is faster than a master clock is provided. A voltage comparator compares a pixel signal input from a vertical signal line for each row control line with a reference voltage, generating pulses having magnitudes corresponding to a reset component or a signal component in a temporal direction. A counter counts the width of pulse signals until completion of the comparison in the voltage comparator based on a clock that is generated based on the high-speed clock, holding a count value at a time of completion of the comparison. A communication and timing controller exercises control so that the voltage comparator performs comparison for the reset component and the counter performs down-counting in a first processing iteration and so that the voltage comparator performs comparison for the signal component and the counter performs up-counting in a second processing iteration.

Dram temperature measurement system

Abstract: A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output, and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto. A method for measuring temperature of a device using a comparator and converting the bitstream of the comparator to a digital output is also given. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

A 0.35 /spl mu/m CMOS comparator circuit for high-speed ADC applications

Abstract: A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the high gain of the inverters, the sampled signals are amplified toward the rail voltages. This comparator is designed and fabricated in a 0.35 /spl mu/m standard digital CMOS technology. Measurement results show a sampling frequency of 1 GHz with 16 mV resolution for a 1 V input signal range and 2 mW power consumption from a 3.3 V supply. The architecture can be scaled down to smaller feature sizes and lower supply voltages.

An improved differential comparator with field effect diode output stage

Abstract: In a field effect diode, carriers of a p–n junction can be modulated on-line. The p and n regions are created by two oppositely biased, and closely spaced, gates in CMOS SOI technology. Using gates as the third terminal, the field effect diode can operate as a switch or as an amplifying element. In this paper, a conventional differential comparator is designed and its performance is compared with a circuit which uses field effect diodes in its output stage. It is shown that the large current sinking and supplying capability of the field effect diode causes this comparator to operate faster than the conventional circuit, consumes less power and covers less chip area.

Switching power supply apparatus and mobile device

Abstract: The value of a current flowing through a coil (L) is determined. The determined current value is converted to a voltage value, which is then inputted to an inverting input terminal of a comparator (4) and compared thereby with a voltage representative of the difference between the value of a feedback output voltage and the value of a reference voltage. A voltage source (20) is provided to the inverting input terminal of the comparator (4) such that an offset voltage is applied to the voltage value inputted to the inverting input terminal of the comparator (4).

Analog to digital converter circuit with offset reduction and image sensor using the same

Abstract: An image sensor may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section of the ADC to amplify the signals supplied to the comparator inputs and thereby reduce the effect of comparator offset on the comparator decision. The comparator section may be an autozeroing comparator section that is capable of performing an offset reduction operation to store offset compensation values at capacitors provided at its inputs. The amplifier section may be an autozeroing amplifier section having one or more amplifier stages that are capable of performing an offset reduction operation to store offset compensation values at capacitors provided at their inputs. Offset compensation may also be implemented using an autozeroing comparator section without a preceding amplifier section. Related methods of operation cause the circuits to perform the offset reduction operations.

Start-up circuit for DC fan

Abstract: A start-up circuit which decreases a start-up current and stabilizes running of a DC fan. The start-up circuit includes a digital-analog converter for convert a digital control signal from a control chip to an analog control signal, a voltage sampling device connected to an output terminal of the digital-analog converter, a comparator, a switching device for controlling start-up of the DC fan, and a feedback device adjusting current passing through the switching device. The comparator includes two input terminals and an output terminal. One input terminal is connected to an output terminal of the voltage sampling device. The switching device is connected to the output terminal of the comparator. An output signal of the switching device is inputted to the other input terminal of the comparator via the feedback device.

Voltage-and temperature-compensated rc oscillator circuit

Abstract: An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

A 1.2 GHz adaptive floating gate comparator with 13-bit resolution

Abstract: We present a high-speed voltage comparator that uses floating gate adaptation to achieve high comparison resolution. The comparator uses nonvolatile charge storage for either offset nulling or automatic programming of a desired offset. We exploit the negative feedback functionality of pFET hot-electron injection to achieve fully automatic offset cancellation. The design has been fabricated in a commercially available 0.35 /spl mu/m process. Experimental results confirm the ability to reduce the variance of the comparator offset 3600/spl times/ and to accurately program a desired offset with maximum observed residue offset of 469 /spl mu/V and standard deviation 199 /spl mu/V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from -1 V to 1 V. The comparator operates at 1.2 GHz with a power consumption of 2.97 mW.

A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters

Abstract: In traditional comparators especially for flash ADCs, one serious problem is the kick back noise, which disturbs the input signal voltages and consequently might cause errors at the outputs of the ADCs. In this paper, we propose a novel CMOS latched comparator with very low kickback noise for high-speed flash ADCs. The proposed comparator separates analog preamplifier from the positive feedback digital dynamic latch so as to reduce the influence of the kickback noise. Simulation results based on a mixed signal CMOS 0.35 /spl mu/m technology show that, this comparator can work at a maximum clock frequency of 500 MHz with very reduced kickback noise compared with conventional architectures.

Analog switch with reduced parasitic bipolar transistor injection

Abstract: According to the invention a well-switching arrangement, with a semiconductor circuit including a switch having an input terminal, an output terminal and a body region and at least one comparator having a first input coupled to at least one of the terminals and a second input coupled to a positive voltage rail, and logic coupled to an output of the comparator and responsive to the output to selectively couple the body-well region to one of the terminals or to the positive voltage rail

Output level voltage regulation

Abstract: A circuit adapting pin output levels to a reference level in which a digital comparator compares an output voltage from an output pin of a device to a reference voltage level. The comparator, relying on the polarity of the comparator output as well as the registered polarity of the comparator output on the previous clock cycle, signals a state machine, which sends a clocked signal to a sense circuit and voltage regulator. The sense circuit may modify a resistance in a switched resistor network, such that the output level is incrementally stepped at clocked intervals towards the reference voltage until the polarity of the error signal reverses. When the output voltage crosses the reference voltage threshold, the comparator flips states and continues to regulate output pin voltage to the reference voltage level.

Comparator circuit having reduced pulse width distortion

Abstract: A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. An output stage is included in the comparator circuit for receiving the difference signal and for generating an output signal of the comparator circuit, the output signal being representative of the difference signal, the output stage having a switching point associated therewith. The comparator circuit further includes a voltage source coupled to the output of the differential amplifier. The voltage source is operative to generate a reference signal for establishing a common-mode voltage of the difference signal generated by the differential amplifier. The reference signal is substantially centered about the switching point of the output stage and substantially tracks the switching point over variations in process, voltage and/or temperature conditions to which the comparator circuit is subjected.

Switch mode power converter

Abstract: A switch mode power converter is provided which includes a switching cell with a supply input, an output and a control input. A summing comparator has first and second differential input pairs and an output. The output is connected to the control input of the switching cell. An oscillator provides a periodic waveform that is applied to a first one of the inputs of the first differential input pair of the summing comparator. An adjustable reference voltage source provides an adjustable reference voltage a predetermined fraction of which is applied to a second one of the inputs of the first differential input pair of the summing comparator. An error amplifier has differential outputs coupled to the second pair of differential inputs of the summing comparator and a differential input pair. A first input of the differential input pair is coupled to the output of the switching cell, and the adjustable reference voltage from the adjustable reference voltage source is applied to a second input of the differential input pair. Thus, the desired DC voltage is scaled to produce a DC reference for the comparator which generates the desired duty cycle for the pulse signal that drives the switching cell, and thus the desired regulated output voltage, with only minor corrections required across the error terminals to correct small parasitic terms.

Hysteresis comparator circuit

Abstract: An input voltage is applied to an inverting input terminal of a comparator having no hysteresis. A first constant voltage is divided by resistors to create a reference voltage. The reference voltage is applied to a non-inverting input terminal of the comparator through a resistor. Only while an output voltage of the comparator is a low level, a predetermined constant current is supplied to a supply point of the reference voltage and a constant current of the same magnitude is absorbed from the non-inverting input terminal of the comparator.

Optical receiver protection circuit

Abstract: An apparatus for optical receiver circuit protection includes a bias source, a bias monitor, and a comparator. The bias source is to provide a bias voltage to an optical receiver. The bias monitor is coupled to measure a current through the optical receiver, where the current changes responsive to received optical energy. A comparator is coupled to the bias monitor, where the comparator has a first state if the current is less than a threshold current level and where the comparator has a second state if the current is greater than the threshold current level. The bias source is coupled to be enabled responsive to the comparator switching to the first state and disabled responsive to the comparator switching to the second state.

Reliability comparator with hysteresis

Abstract: A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.

A 32 GSample/sec SiGe HBT comparator for ultra-high-speed analog-to-digital conversion

Abstract: This paper presents a monolithic master-slave comparator in an ECL configuration with series-gating for ultra-high-speed medium-resolution analog-to-digital conversion. Implemented in a 200 GHz SiGe HBT technology, the complete chip die, including bondpads, is 1.731 /spl times/ 1.141 mm/sup 2/, with the comparator occupying only 0.0226 mm/sup 2/ when integrated as part of an ADC. It dissipates a total of 405 mW from a 3.5 V power supply. Operating with an input frequency of 5 GHz, the circuit can oversample up to 32 GS/s, with input sensitivity ranging from 5 mV/sub pp/ at 15 GS/s to 37 mV/sub pp/ at 32 GS/s. Operating at Nyquist, the comparator can sample up to 30 GS/s, with input sensitivity ranging from 12 mV/sub pp/ at 20 GS/s to 30 mV/sub pp/ at 30 GS/s. To our knowledge, this comparator achieves the best input sensitivity-sampling rate combination when compared with other standalone comparators in literature.

Switching regulator with DC offset (bias) in controller

Abstract: After a current value flowing through a coil L is detected, it is converted into a voltage value, is then inputted to an inverting input terminal of a comparator 4 , and is then compared with a voltage indicating the difference between the value of a fed back output voltage and a reference voltage. A voltage source 20 is provided at the inverting input terminal of the comparator 4 so that an offset voltage is added to the voltage value to be inputted to the inverting input terminal of the comparator 4.

Rotation state detecting device and rotation state detecting method

Abstract: A rotation state detecting device capable of detecting the direction of rotation of a rotating body includes first and second bridge circuits made up of magneto-resistance effect elements, a first comparator for detecting the increasing/decreasing direction of the center point voltage of the first bridge circuit, a second comparator for detecting the increasing/decreasing direction of the center point voltage of the second bridge circuit, a third comparator for detecting the difference between the center point voltage of the first bridge circuit and the center point voltage of the second bridge circuit, and logic value information deriving means for outputting “1” when the logic values of the outputs of the first comparator and the second comparator are both “1”, outputting “0” when they are both “0”, and continuing to output the previous value at other times, the direction of rotation of the rotating body being determined on the basis of a combination of the outputs of the first, second and third comparators and the logic value information deriving means.

Design and application of the novel low-threshold comparator using hysteresis

Abstract: Comparators using hysteresis were widely used in IC design. The paper first introduces the design of the conventional comparator using hysteresis and its disadvantage for the low-threshold compare. Then a novel low-threshold comparator using hysteresis is developed. The threshold and width of the new comparator can be reduced to the mV range, the resolution and the dynamic characteristics are also good. Finally, a typical application of the new comparator using hysteresis is given for the AC-DC control circuit. Its threshold is 50mV and width is 20mV

A low current consumption CMOS latched comparator for body-implanted chip

Abstract: The paper presents a very low-current consumption latched comparator, for use in a medical application, as a component of a delta-sigma (/spl Delta//spl Sigma/) modulator, which takes advantage of the low gate-source voltage by operating in the sub-threshold region. The comparator has been designed using 0.35-/spl mu/m standard CMOS technology, operating with a 1.5 V power supply. The current consumption of the comparator achieved was less than 150 nA in a post-layout simulation.

Comparator-based drivers for LCD displays and the like

Abstract: A comparator-based driver has a configurable inverter that inverts one of the comparator output signals for application to the gate of a driver transistor used to generate the driver output signal. The configurable inverter can be selectively configured to provide any one of at least two different inverter logic threshold levels. In one possible operational scenario, the configurable inverter is configured such that the inverter logic threshold level is equivalent to the comparator's differential common-mode voltage to provide relatively high driver symmetry. The configurable inverter is then configured to provide a different inverter logic threshold level that is greater than the comparator's differential common-mode voltage to inhibit chattering in the driver output signal.

High-speed comparator

Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.

A 0.9 V offset compensated FGMOS comparator

Abstract: A novel low voltage low power fully differential comparator based on the floating gate MOS (FGMOS) operation is presented in this paper. The FGMOS transistor is used to increase the input range and compensate for offset variations simultaneously. The comparator operates with a supply voltage of 0.9 V in a 0.35 /spl mu/m CMOS process. Its power consumption is less than 6.5 /spl mu/W for an 11 MHz clock frequency.

Power factor improvement connection

Abstract: PROBLEM TO BE SOLVED: To provide a power factor improving circuit which can achieve higher efficiency in full load range, without enlarging the circuit scale, in a switching power source. SOLUTION: A multiplier 113 integrates voltage MULT which is obtained by dividing input voltage and voltage which is obtained via a comparator 117 from the voltage MO being obtained by dividing the output voltage. A comparator 112 compares the voltage CS geared to the current flowing to a MOS-FETQ1 with the multiplication results of the multiplier 113. An RS flip flop 115 takes a set reset action, based on the voltage which is obtained via a comparator 116 from the signal z/c signal outputted from the auxiliary winding Nc of the transformer T1 and the comparison results in the comparator 112, and performs the ON/OFF control of the MOS-FETQ1 via a driver 111. An OFF setting circuit 118 selects a current critical action or a current continuous action, based on the output voltage VGS and the z/c signal via an OSMV120. COPYRIGHT: (C)2007,JPO&INPIT